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s/NEW_ID/NEWER_ID/g
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parent
e4d4de1020
commit
d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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@ -121,9 +121,9 @@ struct FmcombineWorker
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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SigSpec gold_q = gold->getPort(ID::Q);
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SigSpec gate_q = gate->getPort(ID::Q);
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SigSpec en = module->Initstate(NEW_ID);
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SigSpec eq = module->Eq(NEW_ID, gold_q, gate_q);
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module->addAssume(NEW_ID, eq, en);
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SigSpec en = module->Initstate(NEWER_ID);
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SigSpec eq = module->Eq(NEWER_ID, gold_q, gate_q);
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module->addAssume(NEWER_ID, eq, en);
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}
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}
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}
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@ -163,7 +163,7 @@ struct FmcombineWorker
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SigSpec A = import_sig(conn.second, "_gold");
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SigSpec B = import_sig(conn.second, "_gate");
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SigBit EQ = module->Eq(NEW_ID, A, B);
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SigBit EQ = module->Eq(NEWER_ID, A, B);
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for (auto bit : sigmap({A, B}))
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data_bit_to_eq_net[bit] = EQ;
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@ -205,7 +205,7 @@ struct FmcombineWorker
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if (GetSize(antecedent) > 1) {
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if (reduce_db.count(antecedent) == 0)
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reduce_db[antecedent] = module->ReduceAnd(NEW_ID, antecedent);
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reduce_db[antecedent] = module->ReduceAnd(NEWER_ID, antecedent);
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antecedent = reduce_db.at(antecedent);
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}
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@ -214,22 +214,22 @@ struct FmcombineWorker
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if (GetSize(consequent) > 1) {
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if (reduce_db.count(consequent) == 0)
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reduce_db[consequent] = module->ReduceAnd(NEW_ID, consequent);
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reduce_db[consequent] = module->ReduceAnd(NEWER_ID, consequent);
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consequent = reduce_db.at(consequent);
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}
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if (opts.fwd)
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module->addAssume(NEW_ID, consequent, antecedent);
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module->addAssume(NEWER_ID, consequent, antecedent);
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if (opts.bwd)
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{
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if (invert_db.count(antecedent) == 0)
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invert_db[antecedent] = module->Not(NEW_ID, antecedent);
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invert_db[antecedent] = module->Not(NEWER_ID, antecedent);
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if (invert_db.count(consequent) == 0)
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invert_db[consequent] = module->Not(NEW_ID, consequent);
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invert_db[consequent] = module->Not(NEWER_ID, consequent);
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module->addAssume(NEW_ID, invert_db.at(antecedent), invert_db.at(consequent));
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module->addAssume(NEWER_ID, invert_db.at(antecedent), invert_db.at(consequent));
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}
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}
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}
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