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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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16
passes/proc/proc_dff.cc
View file

@ -66,16 +66,16 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++)
{
const auto& [sync_value, rule] = *it;
const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEW_ID, rule->signal);
const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEWER_ID, rule->signal);
// If pos_trig is true, we have priority at this point in the tree so
// set a bit if sync_value has a set bit. Otherwise, defer to the rest
// of the priority tree
sig_sr_set = mod->Mux(NEW_ID, sig_sr_set, sync_value, pos_trig);
sig_sr_set = mod->Mux(NEWER_ID, sig_sr_set, sync_value, pos_trig);
// Same deal with clear bit
const auto sync_value_inv = mod->Not(NEW_ID, sync_value);
sig_sr_clr = mod->Mux(NEW_ID, sig_sr_clr, sync_value_inv, pos_trig);
const auto sync_value_inv = mod->Not(NEWER_ID, sync_value);
sig_sr_clr = mod->Mux(NEWER_ID, sig_sr_clr, sync_value_inv, pos_trig);
}
std::stringstream sstr;
@ -217,12 +217,12 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
// (with appropriate negation)
RTLIL::SigSpec triggers;
for (const auto &[_, it] : async_rules)
triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEW_ID, it->signal));
triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEWER_ID, it->signal));
// Put this into the dummy sync rule so it can be treated the same
// as ones coming from the module
single_async_rule.type = RTLIL::SyncType::ST1;
single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers);
single_async_rule.signal = mod->ReduceOr(NEWER_ID, triggers);
single_async_rule.actions.push_back(RTLIL::SigSig(sig, rstval));
// Replace existing rules with this new rule
@ -239,9 +239,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
if (async_rules.size() == 1 && async_rules.front().first == sig) {
const auto& [_, rule] = async_rules.front();
if (rule->type == RTLIL::SyncType::ST1)
insig = mod->Mux(NEW_ID, insig, sig, rule->signal);
insig = mod->Mux(NEWER_ID, insig, sig, rule->signal);
else
insig = mod->Mux(NEW_ID, sig, insig, rule->signal);
insig = mod->Mux(NEWER_ID, sig, insig, rule->signal);
async_rules.clear();
}

10
passes/proc/proc_dlatch.cc
View file

@ -246,20 +246,20 @@ struct proc_dlatch_db_t
if (rule.match == State::S1)
and_bits.append(rule.signal);
else if (rule.match == State::S0)
and_bits.append(module->Not(NEW_ID, rule.signal, false, src));
and_bits.append(module->Not(NEWER_ID, rule.signal, false, src));
else
and_bits.append(module->Eq(NEW_ID, rule.signal, rule.match, false, src));
and_bits.append(module->Eq(NEWER_ID, rule.signal, rule.match, false, src));
}
if (!rule.children.empty()) {
SigSpec or_bits;
for (int k : rule.children)
or_bits.append(make_hold(k, src));
and_bits.append(module->ReduceOr(NEW_ID, or_bits, false, src));
and_bits.append(module->ReduceOr(NEWER_ID, or_bits, false, src));
}
if (GetSize(and_bits) == 2)
and_bits = module->And(NEW_ID, and_bits[0], and_bits[1], false, src);
and_bits = module->And(NEWER_ID, and_bits[0], and_bits[1], false, src);
log_assert(GetSize(and_bits) == 1);
rules_sig[n] = and_bits[0];
@ -429,7 +429,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
SigSpec lhs = latches_bits.first.extract(offset, width);
SigSpec rhs = latches_bits.second.extract(offset, width);
Cell *cell = db.module->addDlatch(NEW_ID, db.module->Not(NEW_ID, db.make_hold(n, src)), rhs, lhs);
Cell *cell = db.module->addDlatch(NEWER_ID, db.module->Not(NEWER_ID, db.make_hold(n, src)), rhs, lhs);
cell->set_src_attribute(src);
db.generated_dlatches.insert(cell);

6
passes/proc/proc_memwr.cc
View file

@ -42,7 +42,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
priority_mask.set(prev_port_ids[i], State::S1);
prev_port_ids.push_back(port_id);
RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2));
RTLIL::Cell *cell = mod->addCell(NEWER_ID, ID($memwr_v2));
cell->attributes = memwr.attributes;
cell->setParam(ID::MEMID, Const(memwr.memid.str()));
cell->setParam(ID::ABITS, GetSize(memwr.address));
@ -55,10 +55,10 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
for (auto sr2 : proc->syncs) {
if (sr2->type == RTLIL::SyncType::ST0) {
log_assert(sr2->mem_write_actions.empty());
enable = mod->Mux(NEW_ID, Const(State::S0, GetSize(enable)), enable, sr2->signal);
enable = mod->Mux(NEWER_ID, Const(State::S0, GetSize(enable)), enable, sr2->signal);
} else if (sr2->type == RTLIL::SyncType::ST1) {
log_assert(sr2->mem_write_actions.empty());
enable = mod->Mux(NEW_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal);
enable = mod->Mux(NEWER_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal);
}
}
cell->setPort(ID::EN, enable);

4
passes/proc/proc_rom.cc
View file

@ -151,8 +151,8 @@ struct RomWorker
}
// Ok, let's do it.
SigSpec rdata = module->addWire(NEW_ID, GetSize(lhs));
Mem mem(module, NEW_ID, GetSize(lhs), 0, 1 << abits);
SigSpec rdata = module->addWire(NEWER_ID, GetSize(lhs));
Mem mem(module, NEWER_ID, GetSize(lhs), 0, 1 << abits);
mem.attributes = sw->attributes;
Const::Builder builder(mem.size * GetSize(lhs));