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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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2
passes/opt/muxpack.cc
View file

@ -283,7 +283,7 @@ struct MuxpackWorker
else {
log_assert(cursor_cell->type == ID($mux));
b_sig.append(cursor_cell->getPort(ID::A));
s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
s_sig.append(module->LogicNot(NEWER_ID, cursor_cell->getPort(ID::S)));
}
remove_cells.insert(cursor_cell);
}

8
passes/opt/opt_demorgan.cc
View file

@ -99,8 +99,8 @@ void demorgan_worker(
//We are NOT inverted! Add an inverter
if(!srcinv)
{
auto inverted_b = m->addWire(NEW_ID);
m->addNot(NEW_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b));
auto inverted_b = m->addWire(NEWER_ID);
m->addNot(NEWER_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b));
insig[i] = inverted_b;
}
@ -166,8 +166,8 @@ void demorgan_worker(
//Add an inverter to the output
auto inverted_output = cell->getPort(ID::Y);
auto uninverted_output = m->addWire(NEW_ID);
m->addNot(NEW_ID, RTLIL::SigSpec(uninverted_output), inverted_output);
auto uninverted_output = m->addWire(NEWER_ID);
m->addNot(NEWER_ID, RTLIL::SigSpec(uninverted_output), inverted_output);
cell->setPort(ID::Y, uninverted_output);
}

60
passes/opt/opt_dff.cc
View file

@ -244,8 +244,8 @@ struct OptDffWorker
s2.append(it.second);
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y);
RTLIL::SigSpec y = module->addWire(NEWER_ID);
RTLIL::Cell *c = module->addNe(NEWER_ID, s1, s2, y);
if (make_gates) {
simplemap(module, c);
@ -258,9 +258,9 @@ struct OptDffWorker
if (item.second)
or_input.append(item.first);
else if (make_gates)
or_input.append(module->NotGate(NEW_ID, item.first));
or_input.append(module->NotGate(NEWER_ID, item.first));
else
or_input.append(module->Not(NEW_ID, item.first));
or_input.append(module->Not(NEWER_ID, item.first));
}
if (GetSize(or_input) == 0)
@ -269,8 +269,8 @@ struct OptDffWorker
if (GetSize(or_input) == 1)
return ctrl_t(or_input, true);
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y);
RTLIL::SigSpec y = module->addWire(NEWER_ID);
RTLIL::Cell *c = module->addReduceAnd(NEWER_ID, or_input, y);
if (make_gates) {
simplemap(module, c);
@ -298,13 +298,13 @@ struct OptDffWorker
if (item.second == final_pol)
or_input.append(item.first);
else if (make_gates)
or_input.append(module->NotGate(NEW_ID, item.first));
or_input.append(module->NotGate(NEWER_ID, item.first));
else
or_input.append(module->Not(NEW_ID, item.first));
or_input.append(module->Not(NEWER_ID, item.first));
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = final_pol ? module->addReduceOr(NEW_ID, or_input, y) : module->addReduceAnd(NEW_ID, or_input, y);
RTLIL::SigSpec y = module->addWire(NEWER_ID);
RTLIL::Cell *c = final_pol ? module->addReduceOr(NEWER_ID, or_input, y) : module->addReduceAnd(NEWER_ID, or_input, y);
if (make_gates) {
simplemap(module, c);
@ -348,9 +348,9 @@ struct OptDffWorker
if (!ff.pol_clr) {
module->connect(ff.sig_q[i], ff.sig_clr[i]);
} else if (ff.is_fine) {
module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNotGate(NEWER_ID, ff.sig_clr[i], ff.sig_q[i]);
} else {
module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNot(NEWER_ID, ff.sig_clr[i], ff.sig_q[i]);
}
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
i, log_id(cell), log_id(cell->type), log_id(module));
@ -451,34 +451,34 @@ struct OptDffWorker
SigSpec tmp;
if (ff.is_fine) {
if (ff.pol_set)
tmp = module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set);
tmp = module->MuxGate(NEWER_ID, ff.sig_ad, State::S1, ff.sig_set);
else
tmp = module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set);
tmp = module->MuxGate(NEWER_ID, State::S1, ff.sig_ad, ff.sig_set);
if (ff.pol_clr)
module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEWER_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);
else
module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEWER_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);
} else {
if (ff.pol_set)
tmp = module->Or(NEW_ID, ff.sig_ad, ff.sig_set);
tmp = module->Or(NEWER_ID, ff.sig_ad, ff.sig_set);
else
tmp = module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set));
tmp = module->Or(NEWER_ID, ff.sig_ad, module->Not(NEWER_ID, ff.sig_set));
if (ff.pol_clr)
module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q);
module->addAnd(NEWER_ID, tmp, module->Not(NEWER_ID, ff.sig_clr), ff.sig_q);
else
module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q);
module->addAnd(NEWER_ID, tmp, ff.sig_clr, ff.sig_q);
}
} else if (ff.has_arst) {
if (ff.is_fine) {
if (ff.pol_arst)
module->addMuxGate(NEW_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q);
module->addMuxGate(NEWER_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q);
else
module->addMuxGate(NEW_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q);
module->addMuxGate(NEWER_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q);
} else {
if (ff.pol_arst)
module->addMux(NEW_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q);
module->addMux(NEWER_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q);
else
module->addMux(NEW_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q);
module->addMux(NEWER_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q);
}
} else {
module->connect(ff.sig_q, ff.sig_ad);
@ -594,20 +594,20 @@ struct OptDffWorker
if (ff.has_ce && ff.ce_over_srst) {
if (!ff.pol_ce) {
if (ff.is_fine)
ff.sig_ce = module->NotGate(NEW_ID, ff.sig_ce);
ff.sig_ce = module->NotGate(NEWER_ID, ff.sig_ce);
else
ff.sig_ce = module->Not(NEW_ID, ff.sig_ce);
ff.sig_ce = module->Not(NEWER_ID, ff.sig_ce);
}
if (!ff.pol_srst) {
if (ff.is_fine)
ff.sig_srst = module->NotGate(NEW_ID, ff.sig_srst);
ff.sig_srst = module->NotGate(NEWER_ID, ff.sig_srst);
else
ff.sig_srst = module->Not(NEW_ID, ff.sig_srst);
ff.sig_srst = module->Not(NEWER_ID, ff.sig_srst);
}
if (ff.is_fine)
ff.sig_ce = module->AndGate(NEW_ID, ff.sig_ce, ff.sig_srst);
ff.sig_ce = module->AndGate(NEWER_ID, ff.sig_ce, ff.sig_srst);
else
ff.sig_ce = module->And(NEW_ID, ff.sig_ce, ff.sig_srst);
ff.sig_ce = module->And(NEWER_ID, ff.sig_ce, ff.sig_srst);
ff.pol_ce = true;
} else {
ff.pol_ce = ff.pol_srst;

68
passes/opt/opt_expr.cc
View file

@ -202,7 +202,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
if (grouped_bits[i].empty())
continue;
RTLIL::SigSpec new_y = module->addWire(NEW_ID, GetSize(grouped_bits[i]));
RTLIL::SigSpec new_y = module->addWire(NEWER_ID, GetSize(grouped_bits[i]));
RTLIL::SigSpec new_a, new_b;
RTLIL::SigSig new_conn;
@ -247,9 +247,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
else if (new_a[i] == State::S0 || new_a[i] == State::S1) {
undef_a.append(new_a[i]);
if (cell->type == ID($xor))
undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID, new_b[i]).as_bit() : new_b[i]);
undef_b.append(new_a[i] == State::S1 ? module->Not(NEWER_ID, new_b[i]).as_bit() : new_b[i]);
else if (cell->type == ID($xnor))
undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID, new_b[i]).as_bit());
undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEWER_ID, new_b[i]).as_bit());
else log_abort();
undef_y.append(new_y[i]);
}
@ -273,7 +273,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
}
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
RTLIL::Cell *c = module->addCell(NEWER_ID, cell->type);
c->setPort(ID::A, new_a);
c->parameters[ID::A_WIDTH] = new_a.size();
@ -612,9 +612,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.xor_buffer");
SigSpec sig_y;
if (cell->type == ID($xor))
sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a);
sig_y = (sig_b == State::S1 ? module->Not(NEWER_ID, sig_a).as_bit() : sig_a);
else if (cell->type == ID($_XOR_))
sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
sig_y = (sig_b == State::S1 ? module->NotGate(NEWER_ID, sig_a) : sig_a);
else log_abort();
replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y);
goto next_cell;
@ -623,12 +623,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.xnor_buffer");
SigSpec sig_y;
if (cell->type == ID($xnor)) {
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit());
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEWER_ID, sig_a).as_bit());
int width = cell->getParam(ID::Y_WIDTH).as_int();
sig_y.append(RTLIL::Const(State::S1, width-1));
}
else if (cell->type == ID($_XNOR_))
sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a));
sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEWER_ID, sig_a));
else log_abort();
replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y);
goto next_cell;
@ -698,7 +698,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!y_group_1.empty()) y_new_1 = b_group_1;
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->And(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->And(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
else
y_new_x = Const(State::S0, GetSize(y_group_x));
}
@ -707,16 +707,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!y_group_1.empty()) y_new_1 = Const(State::S1, GetSize(y_group_1));
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->Or(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->Or(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
else
y_new_x = Const(State::S1, GetSize(y_group_x));
}
} else if (cell->type.in(ID($xor), ID($xnor))) {
if (!y_group_0.empty()) y_new_0 = b_group_0;
if (!y_group_1.empty()) y_new_1 = module->Not(NEW_ID, b_group_1);
if (!y_group_1.empty()) y_new_1 = module->Not(NEWER_ID, b_group_1);
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->Xor(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->Xor(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor
y_new_x = Const(State::Sx, GetSize(y_group_x));
}
@ -779,11 +779,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec y_new_0, y_new_1;
if (flip) {
if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, module->Not(NEW_ID, s_group_0));
if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, s_group_1);
if (!y_group_0.empty()) y_new_0 = module->And(NEWER_ID, b_group_0, module->Not(NEWER_ID, s_group_0));
if (!y_group_1.empty()) y_new_1 = module->Or(NEWER_ID, b_group_1, s_group_1);
} else {
if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, s_group_0);
if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, module->Not(NEW_ID, s_group_1));
if (!y_group_0.empty()) y_new_0 = module->And(NEWER_ID, b_group_0, s_group_0);
if (!y_group_1.empty()) y_new_1 = module->Or(NEWER_ID, b_group_1, module->Not(NEWER_ID, s_group_1));
}
module->connect(y_group_0, y_new_0);
@ -996,12 +996,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigBit a = sig_a[i];
if (b == ((bi ^ ci) ? State::S1 : State::S0)) {
module->connect(sig_y[i], a);
module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a);
module->connect(sig_x[i], ci ? module->Not(NEWER_ID, a).as_bit() : a);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else if (a == (ci ? State::S1 : State::S0)) {
module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_y[i], bi ? module->Not(NEWER_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEWER_ID, b).as_bit() : b);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else
@ -1428,7 +1428,7 @@ skip_fine_alu:
/* sub, b is 0 */
RTLIL::SigSpec a = cell->getPort(ID::A);
a.extend_u0(y_width, is_signed);
module->connect(cell->getPort(ID::X), module->Not(NEW_ID, a));
module->connect(cell->getPort(ID::X), module->Not(NEWER_ID, a));
module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S1, y_width));
} else {
/* add */
@ -1733,10 +1733,10 @@ skip_identity:
cell->parameters[ID::A_SIGNED] = 0;
cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int()));
SigSpec y_wire = module->addWire(NEW_ID, y_size);
SigSpec y_wire = module->addWire(NEWER_ID, y_size);
cell->setPort(ID::Y, y_wire);
module->addShl(NEW_ID, Const(State::S1, 1), y_wire, sig_y);
module->addShl(NEWER_ID, Const(State::S1, 1), y_wire, sig_y);
}
did_something = true;
goto next_cell;
@ -1889,13 +1889,13 @@ skip_identity:
// Truncating division is the same as flooring division, except when
// the result is negative and there is a remainder - then trunc = floor + 1
if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) {
Wire *flooring = module->addWire(NEW_ID, sig_y.size());
Wire *flooring = module->addWire(NEWER_ID, sig_y.size());
cell->setPort(ID::Y, flooring);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero);
module->addAdd(NEW_ID, flooring, should_add, sig_y);
SigSpec rem_nonzero = module->ReduceOr(NEWER_ID, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEWER_ID, a_sign, rem_nonzero);
module->addAdd(NEWER_ID, flooring, should_add, sig_y);
}
cell->check();
@ -1917,11 +1917,11 @@ skip_identity:
SigSpec truncating = sig_a.extract(0, exp);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec extend_bit = module->And(NEW_ID, a_sign, rem_nonzero);
SigSpec rem_nonzero = module->ReduceOr(NEWER_ID, sig_a.extract(0, exp));
SigSpec extend_bit = module->And(NEWER_ID, a_sign, rem_nonzero);
truncating.append(extend_bit);
module->addPos(NEW_ID, truncating, sig_y, true);
module->addPos(NEWER_ID, truncating, sig_y, true);
}
else
{
@ -2004,7 +2004,7 @@ skip_identity:
int sz = cur - prev;
bool last = cur == GetSize(sig_y);
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
RTLIL::Cell *c = module->addCell(NEWER_ID, cell->type);
c->setPort(ID::A, sig_a.extract(prev, sz));
c->setPort(ID::B, sig_b.extract(prev, sz));
c->setPort(ID::BI, sig_bi);
@ -2014,7 +2014,7 @@ skip_identity:
RTLIL::SigSpec new_co = sig_co.extract(prev, sz);
if (p.second != State::Sx) {
module->connect(new_co[sz-1], p.second);
RTLIL::Wire *dummy = module->addWire(NEW_ID);
RTLIL::Wire *dummy = module->addWire(NEWER_ID);
new_co[sz-1] = dummy;
}
c->setPort(ID::CO, new_co);
@ -2181,14 +2181,14 @@ skip_alu_split:
{
condition = stringf("unsigned X<%s", log_signal(const_sig));
replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
module->addLogicNot(NEW_ID, var_high_sig, cell->getPort(ID::Y));
module->addLogicNot(NEWER_ID, var_high_sig, cell->getPort(ID::Y));
remove = true;
}
if (cmp_type == ID($ge))
{
condition = stringf("unsigned X>=%s", log_signal(const_sig));
replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
module->addReduceOr(NEW_ID, var_high_sig, cell->getPort(ID::Y));
module->addReduceOr(NEWER_ID, var_high_sig, cell->getPort(ID::Y));
remove = true;
}
}
@ -2230,7 +2230,7 @@ skip_alu_split:
{
condition = "signed X>=0";
replacement = stringf("X[%d]", var_width - 1);
module->addLogicNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID::Y));
module->addLogicNot(NEWER_ID, var_sig[var_width - 1], cell->getPort(ID::Y));
remove = true;
}
}

4
passes/opt/opt_hier.cc
View file

@ -137,7 +137,7 @@ struct ModuleIndex {
rhs.replace(constant_outputs);
log_assert(rhs.is_fully_const());
parent.module->connect(value.extract(chunk.offset, chunk.width), rhs);
SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("const_output"), chunk.width);
SigSpec dummy = parent.module->addWire(NEWER_ID_SUFFIX("const_output"), chunk.width);
for (int i = 0; i < chunk.width; i++)
value[chunk.offset + i] = dummy[i];
}
@ -182,7 +182,7 @@ struct ModuleIndex {
severed_port_bits.sort_and_unify();
for (auto chunk : severed_port_bits.chunks()) {
SigSpec &value = instantiation->connections_.at(chunk.wire->name);
SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("tie_together"), chunk.width);
SigSpec dummy = parent.module->addWire(NEWER_ID_SUFFIX("tie_together"), chunk.width);
for (int i = 0; i < chunk.width; i++)
value[chunk.offset + i] = dummy[i];
}

2
passes/opt/opt_mem.cc
View file

@ -125,7 +125,7 @@ struct OptMemPass : public Pass {
module->connect(port.data[bidx], bit);
} else {
// The FF will most likely be redundant, but it's up to opt_dff to deal with this.
FfData ff(module, &initvals, NEW_ID);
FfData ff(module, &initvals, NEWER_ID);
ff.width = 1;
ff.has_clk = true;
ff.sig_clk = port.clk;

4
passes/opt/opt_mem_feedback.cc
View file

@ -120,7 +120,7 @@ struct OptMemFeedbackWorker
sig1.append(it.first);
sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0);
}
terms.append(module->Ne(NEW_ID, sig1, sig2));
terms.append(module->Ne(NEWER_ID, sig1, sig2));
}
if (olden != State::S1)
@ -130,7 +130,7 @@ struct OptMemFeedbackWorker
terms = State::S1;
if (GetSize(terms) > 1)
terms = module->ReduceAnd(NEW_ID, terms);
terms = module->ReduceAnd(NEWER_ID, terms);
return conditions_logic_cache[key] = terms;
}

4
passes/opt/opt_reduce.cc
View file

@ -128,13 +128,13 @@ struct OptReduceWorker
if (this_s.size() > 1)
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
RTLIL::Cell *reduce_or_cell = module->addCell(NEWER_ID, ID($reduce_or));
reduce_or_cell->setPort(ID::A, this_s);
reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
RTLIL::Wire *reduce_or_wire = module->addWire(NEWER_ID);
this_s = RTLIL::SigSpec(reduce_or_wire);
reduce_or_cell->setPort(ID::Y, this_s);
}

12
passes/opt/opt_share.cc
View file

@ -196,7 +196,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
for (auto &operand : muxed_operands) {
operand.sig.extend_u0(max_width, operand.is_signed);
if (operand.sign != muxed_operands[0].sign)
operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
operand = ExtSigSpec(module->Neg(NEWER_ID, operand.sig, operand.is_signed));
}
for (const auto& p : ports) {
@ -219,7 +219,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
RTLIL::SigSpec shared_pmux_s;
// Make a new wire to avoid false equivalence with whatever the former shared output was connected to.
Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width);
Wire *new_out = module->addWire(NEWER_ID, conn_op_offset + conn_width);
SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width);
for (int i = 0; i < GetSize(ports); i++) {
@ -241,14 +241,14 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
SigSpec mux_to_oper;
if (GetSize(shared_pmux_s) == 1) {
mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
mux_to_oper = module->Mux(NEWER_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
} else {
mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
mux_to_oper = module->Pmux(NEWER_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
}
if (shared_op->type.in(ID($alu))) {
shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(ID::X, module->addWire(NEWER_ID, GetSize(new_out)));
shared_op->setPort(ID::CO, module->addWire(NEWER_ID, GetSize(new_out)));
}
bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);

4
passes/opt/peepopt_formal_clockgateff.pmg
View file

@ -50,8 +50,8 @@ code
// instead of the latch. We don't delete the latch in case its output is
// used to drive other nodes. If it isn't, it will be trivially removed by
// clean
SigSpec flopped_en = module->addWire(NEW_ID);
module->addDff(NEW_ID, clk, en, flopped_en, true, latch->get_src_attribute());
SigSpec flopped_en = module->addWire(NEWER_ID);
module->addDff(NEWER_ID, clk, en, flopped_en, true, latch->get_src_attribute());
and_gate->setPort(latched_en_port_name, flopped_en);
did_something = true;

6
passes/opt/peepopt_shiftmul_left.pmg
View file

@ -129,7 +129,7 @@ code
if (bit == SigBit(State::Sm))
padbits++;
SigSpec padwire = module->addWire(NEW_ID, padbits);
SigSpec padwire = module->addWire(NEWER_ID, padbits);
for (int i = new_y.size() - 1; i >= 0; i--)
if (new_y[i] == SigBit(State::Sm)) {
@ -148,8 +148,8 @@ code
shift->setPort(\B, new_b);
shift->setParam(\B_WIDTH, GetSize(new_b));
} else {
SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1);
module->addNeg(NEW_ID, new_b, b_neg);
SigSpec b_neg = module->addWire(NEWER_ID, GetSize(new_b) + 1);
module->addNeg(NEWER_ID, new_b, b_neg);
shift->setPort(\B, b_neg);
shift->setParam(\B_WIDTH, GetSize(b_neg));
}

12
passes/opt/pmux2shiftx.cc
View file

@ -680,9 +680,9 @@ struct Pmux2ShiftxPass : public Pass {
// creat cmp signal
SigSpec cmp = perm_sig;
if (perm_xormask.as_bool())
cmp = module->Xor(NEW_ID, cmp, perm_xormask, false, src);
cmp = module->Xor(NEWER_ID, cmp, perm_xormask, false, src);
if (offset.as_bool())
cmp = module->Sub(NEW_ID, cmp, offset, false, src);
cmp = module->Sub(NEWER_ID, cmp, offset, false, src);
// create enable signal
SigBit en = State::S1;
@ -690,8 +690,8 @@ struct Pmux2ShiftxPass : public Pass {
Const enable_mask(State::S0, max_choice+1);
for (auto &it : perm_choices)
enable_mask.set(it.first.as_int(), State::S1);
en = module->addWire(NEW_ID);
module->addShift(NEW_ID, enable_mask, cmp, en, false, src);
en = module->addWire(NEWER_ID);
module->addShift(NEWER_ID, enable_mask, cmp, en, false, src);
}
// create data signal
@ -710,8 +710,8 @@ struct Pmux2ShiftxPass : public Pass {
// create shiftx cell
SigSpec shifted_cmp = {cmp, SigSpec(State::S0, width_bits)};
SigSpec outsig = module->addWire(NEW_ID, width);
Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src);
SigSpec outsig = module->addWire(NEWER_ID, width);
Cell *c = module->addShiftx(NEWER_ID, data, shifted_cmp, outsig, false, src);
updated_S.append(en);
updated_B.append(outsig);
log(" created $shiftx cell %s.\n", log_id(c));

92
passes/opt/share.cc
View file

@ -207,13 +207,13 @@ struct ShareWorker
sig_b2.extend_u0(GetSize(sig_b), p2.is_signed);
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, sig_a2, sig_a1, act, sig_a));
sig_a = module->addWire(NEWER_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEWER_ID, sig_a2, sig_a1, act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b));
sig_b = module->addWire(NEWER_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEWER_ID, sig_b2, sig_b1, act, sig_b));
}
Macc::term_t p;
@ -284,13 +284,13 @@ struct ShareWorker
RTLIL::SigSpec sig_b = m1.terms[i].in_b;
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a));
sig_a = module->addWire(NEWER_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEWER_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b));
sig_b = module->addWire(NEWER_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEWER_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b));
}
Macc::term_t p;
@ -307,13 +307,13 @@ struct ShareWorker
RTLIL::SigSpec sig_b = m2.terms[i].in_b;
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a));
sig_a = module->addWire(NEWER_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEWER_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b));
sig_b = module->addWire(NEWER_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEWER_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b));
}
Macc::term_t p;
@ -326,10 +326,10 @@ struct ShareWorker
if (supercell)
{
RTLIL::SigSpec sig_y = module->addWire(NEW_ID, width);
RTLIL::SigSpec sig_y = module->addWire(NEWER_ID, width);
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEWER_ID, sig_y, c1->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEWER_ID, sig_y, c2->getPort(ID::Y)));
supercell->setParam(ID::Y_WIDTH, width);
supercell->setPort(ID::Y, sig_y);
@ -541,20 +541,20 @@ struct ShareWorker
a1.extend_u0(a_width, a_signed);
a2.extend_u0(a_width, a_signed);
RTLIL::SigSpec a = module->addWire(NEW_ID, a_width);
supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a));
RTLIL::SigSpec a = module->addWire(NEWER_ID, a_width);
supercell_aux.insert(module->addMux(NEWER_ID, a2, a1, act, a));
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Wire *y = module->addWire(NEWER_ID, y_width);
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1->type);
supercell->parameters[ID::A_SIGNED] = a_signed;
supercell->parameters[ID::A_WIDTH] = a_width;
supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a);
supercell->setPort(ID::Y, y);
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
supercell_aux.insert(module->addPos(NEWER_ID, y, y1));
supercell_aux.insert(module->addPos(NEWER_ID, y, y2));
supercell_aux.insert(supercell);
return supercell;
@ -656,17 +656,17 @@ struct ShareWorker
b1.extend_u0(b_width, b_signed);
b2.extend_u0(b_width, b_signed);
RTLIL::SigSpec a = module->addWire(NEW_ID, a_width);
RTLIL::SigSpec b = module->addWire(NEW_ID, b_width);
RTLIL::SigSpec a = module->addWire(NEWER_ID, a_width);
RTLIL::SigSpec b = module->addWire(NEWER_ID, b_width);
supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a));
supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b));
supercell_aux.insert(module->addMux(NEWER_ID, a2, a1, act, a));
supercell_aux.insert(module->addMux(NEWER_ID, b2, b1, act, b));
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Wire *y = module->addWire(NEWER_ID, y_width);
RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEWER_ID, y_width) : nullptr;
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEWER_ID, y_width) : nullptr;
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1->type);
supercell->parameters[ID::A_SIGNED] = a_signed;
supercell->parameters[ID::B_SIGNED] = b_signed;
supercell->parameters[ID::A_WIDTH] = a_width;
@ -676,9 +676,9 @@ struct ShareWorker
supercell->setPort(ID::B, b);
supercell->setPort(ID::Y, y);
if (c1->type == ID($alu)) {
RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID);
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci));
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi));
RTLIL::Wire *ci = module->addWire(NEWER_ID), *bi = module->addWire(NEWER_ID);
supercell_aux.insert(module->addMux(NEWER_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci));
supercell_aux.insert(module->addMux(NEWER_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi));
supercell->setPort(ID::CI, ci);
supercell->setPort(ID::BI, bi);
supercell->setPort(ID::CO, co);
@ -686,13 +686,13 @@ struct ShareWorker
}
supercell->check();
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
supercell_aux.insert(module->addPos(NEWER_ID, y, y1));
supercell_aux.insert(module->addPos(NEWER_ID, y, y2));
if (c1->type == ID($alu)) {
supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEWER_ID, co, c1->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEWER_ID, co, c2->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEWER_ID, x, c1->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEWER_ID, x, c2->getPort(ID::X)));
}
supercell_aux.insert(supercell);
@ -701,7 +701,7 @@ struct ShareWorker
if (c1->type == ID($macc))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1->type);
supercell_aux.insert(supercell);
share_macc(c1, c2, act, supercell, &supercell_aux);
supercell->check();
@ -710,16 +710,16 @@ struct ShareWorker
if (c1->type.in(ID($memrd), ID($memrd_v2)))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1);
RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR);
RTLIL::SigSpec addr2 = c2->getPort(ID::ADDR);
if (GetSize(addr1) < GetSize(addr2))
addr1.extend_u0(GetSize(addr2));
else
addr2.extend_u0(GetSize(addr1));
supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEWER_ID, addr2, addr1, act) : addr1);
supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1));
supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA)));
supercell_aux.insert(module->addPos(NEWER_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA)));
supercell_aux.insert(supercell);
return supercell;
}
@ -1065,18 +1065,18 @@ struct ShareWorker
RTLIL::SigSpec make_cell_activation_logic(const pool<ssc_pair_t> &activation_patterns, pool<RTLIL::Cell*> &supercell_aux)
{
RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
RTLIL::Wire *all_cases_wire = module->addWire(NEWER_ID, 0);
for (auto &p : activation_patterns) {
all_cases_wire->width++;
supercell_aux.insert(module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1)));
supercell_aux.insert(module->addEq(NEWER_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1)));
}
if (all_cases_wire->width == 1)
return all_cases_wire;
RTLIL::Wire *result_wire = module->addWire(NEW_ID);
supercell_aux.insert(module->addReduceOr(NEW_ID, all_cases_wire, result_wire));
RTLIL::Wire *result_wire = module->addWire(NEWER_ID);
supercell_aux.insert(module->addReduceOr(NEWER_ID, all_cases_wire, result_wire));
return result_wire;
}

2
passes/opt/wreduce.cc
View file

@ -511,7 +511,7 @@ struct WreduceWorker
continue;
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
Wire *nw = module->addWire(NEWER_ID, GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
}