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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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10
passes/cmds/splice.cc
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@ -75,12 +75,12 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($slice));
cell->parameters[ID::OFFSET] = offset;
cell->parameters[ID::A_WIDTH] = sig_a.size();
cell->parameters[ID::Y_WIDTH] = sig.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
cell->setPort(ID::Y, module->addWire(NEWER_ID, sig.size()));
new_sig = cell->getPort(ID::Y);
}
@ -132,12 +132,12 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($concat));
cell->parameters[ID::A_WIDTH] = new_sig.size();
cell->parameters[ID::B_WIDTH] = sig2.size();
cell->setPort(ID::A, new_sig);
cell->setPort(ID::B, sig2);
cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));
cell->setPort(ID::Y, module->addWire(NEWER_ID, new_sig.size() + sig2.size()));
new_sig = cell->getPort(ID::Y);
}
@ -232,7 +232,7 @@ struct SpliceWorker
for (auto &it : rework_wires)
{
RTLIL::IdString orig_name = it.first->name;
module->rename(it.first, NEW_ID);
module->rename(it.first, NEWER_ID);
RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
it.first->port_id = 0;