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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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16
passes/cmds/abstract.cc
View file

@ -82,7 +82,7 @@ struct Slice {
};
void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_output, EnableLogic enable) {
auto anyseq = mod->Anyseq(NEW_ID, mux_input.size());
auto anyseq = mod->Anyseq(NEWER_ID, mux_input.size());
if (enable.bit == (enable.pol ? State::S1 : State::S0)) {
mod->connect(mux_output, anyseq);
}
@ -94,7 +94,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o
mux_a = anyseq;
mux_b = mux_input;
}
(void)mod->addMux(NEW_ID,
(void)mod->addMux(NEWER_ID,
mux_a,
mux_b,
enable.bit,
@ -102,7 +102,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o
}
bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, EnableLogic enable) {
Wire* abstracted = ff.module->addWire(NEW_ID, offsets.size());
Wire* abstracted = ff.module->addWire(NEWER_ID, offsets.size());
SigSpec mux_input;
int abstracted_idx = 0;
for (int d_idx = 0; d_idx < ff.width; d_idx++) {
@ -213,7 +213,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector<S
}
bool abstract_value_cell_port(Module* mod, Cell* cell, std::set<int> offsets, IdString port_name, EnableLogic enable) {
Wire* to_abstract = mod->addWire(NEW_ID, offsets.size());
Wire* to_abstract = mod->addWire(NEWER_ID, offsets.size());
SigSpec mux_input;
SigSpec mux_output;
const SigSpec& old_port = cell->getPort(port_name);
@ -235,7 +235,7 @@ bool abstract_value_cell_port(Module* mod, Cell* cell, std::set<int> offsets, Id
}
bool abstract_value_mod_port(Module* mod, Wire* wire, std::set<int> offsets, EnableLogic enable) {
Wire* to_abstract = mod->addWire(NEW_ID, wire);
Wire* to_abstract = mod->addWire(NEWER_ID, wire);
to_abstract->port_input = true;
to_abstract->port_id = wire->port_id;
wire->port_input = false;
@ -501,10 +501,10 @@ struct AbstractPass : public Pass {
enable_logic = { enable_wire, enable == Enable::ActiveHigh };
} break;
case Enable::Initstates: {
SigBit in_init_states = mod->Initstate(NEW_ID);
SigBit in_init_states = mod->Initstate(NEWER_ID);
for (int i = 1; i < initstates; i++) {
Wire *in_init_states_q = mod->addWire(NEW_ID);
mod->addFf(NEW_ID, in_init_states, in_init_states_q);
Wire *in_init_states_q = mod->addWire(NEWER_ID);
mod->addFf(NEWER_ID, in_init_states, in_init_states_q);
in_init_states_q->attributes[ID::init] = State::S1;
in_init_states = in_init_states_q;
}

2
passes/cmds/add.cc
View file

@ -41,7 +41,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
log_error("Could not find wire with name \"%s\".\n", name);
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
RTLIL::Cell *formal_cell = module->addCell(NEWER_ID, "$" + celltype);
formal_cell->setPort(ID::A, wire);
if(enable_name == "") {
formal_cell->setPort(ID::EN, State::S1);

2
passes/cmds/bugpoint.cc
View file

@ -304,7 +304,7 @@ struct BugpointPass : public Pass {
if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
{
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", log_id(mod), log_id(cell), log_id(it.first));
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
RTLIL::Wire *wire = mod->addWire(NEWER_ID, port.size());
wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first);
wire->port_output = cell->output(it.first);

24
passes/cmds/chformal.cc
View file

@ -337,12 +337,12 @@ struct ChformalPass : public Pass {
SigSpec orig_a = cell->getPort(ID::A);
SigSpec orig_en = cell->getPort(ID::EN);
Wire *new_a = module->addWire(NEW_ID);
Wire *new_en = module->addWire(NEW_ID);
Wire *new_a = module->addWire(NEWER_ID);
Wire *new_en = module->addWire(NEWER_ID);
new_en->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, orig_a, new_a);
module->addFf(NEW_ID, orig_en, new_en);
module->addFf(NEWER_ID, orig_a, new_a);
module->addFf(NEWER_ID, orig_en, new_en);
cell->setPort(ID::A, new_a);
cell->setPort(ID::EN, new_en);
@ -355,14 +355,14 @@ struct ChformalPass : public Pass {
SigSpec en = State::S1;
for (int i = 0; i < mode_arg; i++) {
Wire *w = module->addWire(NEW_ID);
Wire *w = module->addWire(NEWER_ID);
w->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, en, w);
module->addFf(NEWER_ID, en, w);
en = w;
}
for (auto cell : constr_cells)
cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
cell->setPort(ID::EN, module->LogicAnd(NEWER_ID, en, cell->getPort(ID::EN)));
}
else
if (mode =='p')
@ -370,7 +370,7 @@ struct ChformalPass : public Pass {
for (auto cell : constr_cells)
{
if (cell->type == ID($check)) {
Cell *cover = module->addCell(NEW_ID_SUFFIX("coverenable"), ID($check));
Cell *cover = module->addCell(NEWER_ID_SUFFIX("coverenable"), ID($check));
cover->attributes = cell->attributes;
cover->parameters = cell->parameters;
cover->setParam(ID(FLAVOR), Const("cover"));
@ -381,7 +381,7 @@ struct ChformalPass : public Pass {
cover->setPort(ID::A, cell->getPort(ID::EN));
cover->setPort(ID::EN, State::S1);
} else {
module->addCover(NEW_ID_SUFFIX("coverenable"),
module->addCover(NEWER_ID_SUFFIX("coverenable"),
cell->getPort(ID::EN), State::S1, cell->get_src_attribute());
}
}
@ -414,7 +414,7 @@ struct ChformalPass : public Pass {
log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell));
Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell));
Cell *plain_cell = module->addCell(NEWER_ID, formal_flavor(cell));
plain_cell->attributes = cell->attributes;
@ -425,9 +425,9 @@ struct ChformalPass : public Pass {
plain_cell->setPort(ID::EN, sig_en);
if (plain_cell->type.in(ID($assert), ID($assume)))
sig_a = module->Not(NEW_ID, sig_a);
sig_a = module->Not(NEWER_ID, sig_a);
SigBit combined_en = module->And(NEW_ID, sig_a, sig_en);
SigBit combined_en = module->And(NEWER_ID, sig_a, sig_en);
module->swap_names(cell, plain_cell);

2
passes/cmds/connect.cc
View file

@ -30,7 +30,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
{
CellTypes ct(design);
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
RTLIL::Wire *dummy_wire = module->addWire(NEWER_ID, sig.size());
for (auto cell : module->cells())
for (auto &port : cell->connections_)

84
passes/cmds/dft_tag.cc
View file

@ -101,7 +101,7 @@ struct DftTagWorker {
log_debug("Applying $overwrite_tag %s for signal %s\n", log_id(cell->name), log_signal(cell->getPort(ID::A)));
SigSpec orig_signal = cell->getPort(ID::A);
SigSpec interposed_signal = divert_users(orig_signal);
auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal);
auto *set_tag_cell = module->addSetTag(NEWER_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal);
modwalker.add_cell(set_tag_cell); // Make sure the next $overwrite_tag sees the new connections
design_changed = true;
}
@ -123,7 +123,7 @@ struct DftTagWorker {
signal_mapped.sort_and_unify();
if (GetSize(signal_mapped) < GetSize(signal))
log_warning("Detected $overwrite_tag on signal %s which contains repeated bits, this can result in unexpected behavior.\n", log_signal(signal));
SigSpec new_wire = module->addWire(NEW_ID, GetSize(signal));
SigSpec new_wire = module->addWire(NEWER_ID, GetSize(signal));
for (int i = 0; i < GetSize(new_wire); ++i)
divert_users(signal[i], new_wire[i]);
return new_wire;
@ -318,7 +318,7 @@ struct DftTagWorker {
if (!GetSize(combined))
combined = tag_sig;
else
combined = autoOr(NEW_ID, combined, tag_sig);
combined = autoOr(NEWER_ID, combined, tag_sig);
}
if (!GetSize(combined))
@ -359,7 +359,7 @@ struct DftTagWorker {
// when the outer call for this tag/cell returns
for (auto &conn : cell->connections())
if (cell->output(conn.first))
emit_tag_signal(tag, conn.second, module->addWire(NEW_ID, GetSize(conn.second)));
emit_tag_signal(tag, conn.second, module->addWire(NEWER_ID, GetSize(conn.second)));
return;
}
@ -486,8 +486,8 @@ struct DftTagWorker {
if (cell_tag == tag) {
auto &sig_set = cell->getPort(ID::SET);
auto &sig_clr = cell->getPort(ID::CLR);
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr));
tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set);
tag_sig_a = autoAnd(NEWER_ID, tag_sig_a, autoNot(NEWER_ID, sig_clr));
tag_sig_a = autoOr(NEWER_ID, tag_sig_a, sig_set);
}
emit_tag_signal(tag, sig_y, tag_sig_a);
@ -529,9 +529,9 @@ struct DftTagWorker {
inv_b ^= true;
if (inv_a)
sig_a = autoNot(NEW_ID, sig_a);
sig_a = autoNot(NEWER_ID, sig_a);
if (inv_b)
sig_b = autoNot(NEW_ID, sig_b);
sig_b = autoNot(NEWER_ID, sig_b);
auto group_sig_a = tag_group_signal(tag, sig_a);
auto group_sig_b = tag_group_signal(tag, sig_b);
@ -541,15 +541,15 @@ struct DftTagWorker {
// Does this input allow propagating (doesn't fix output or same tag group)
sig_a = autoOr(NEW_ID, sig_a, group_sig_a);
sig_b = autoOr(NEW_ID, sig_b, group_sig_b);
sig_a = autoOr(NEWER_ID, sig_a, group_sig_a);
sig_b = autoOr(NEWER_ID, sig_b, group_sig_b);
// Mask input tags by whether the other side allows propagation
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, sig_b);
tag_sig_b = autoAnd(NEW_ID, tag_sig_b, sig_a);
tag_sig_a = autoAnd(NEWER_ID, tag_sig_a, sig_b);
tag_sig_b = autoAnd(NEWER_ID, tag_sig_b, sig_a);
auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b);
auto tag_sig = autoOr(NEWER_ID, tag_sig_a, tag_sig_b);
emit_tag_signal(tag, sig_y, tag_sig);
return;
}
@ -566,7 +566,7 @@ struct DftTagWorker {
auto tag_sig_a = tag_signal(tag, sig_a);
auto tag_sig_b = tag_signal(tag, sig_b);
auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b);
auto tag_sig = autoOr(NEWER_ID, tag_sig_a, tag_sig_b);
emit_tag_signal(tag, sig_y, tag_sig);
return;
}
@ -585,23 +585,23 @@ struct DftTagWorker {
auto group_sig_b = tag_group_signal(tag, sig_b);
auto group_sig_s = tag_group_signal(tag, sig_s);
auto prop_s = autoOr(NEW_ID,
autoXor(NEW_ID, sig_a, sig_b),
autoOr(NEW_ID, group_sig_a, group_sig_b));
auto prop_s = autoOr(NEWER_ID,
autoXor(NEWER_ID, sig_a, sig_b),
autoOr(NEWER_ID, group_sig_a, group_sig_b));
auto prop_a = autoOr(NEW_ID, autoNot(NEW_ID, sig_s), group_sig_s);
auto prop_b = autoOr(NEW_ID, sig_s, group_sig_s);
auto prop_a = autoOr(NEWER_ID, autoNot(NEWER_ID, sig_s), group_sig_s);
auto prop_b = autoOr(NEWER_ID, sig_s, group_sig_s);
auto tag_sig_a = tag_signal(tag, sig_a);
auto tag_sig_b = tag_signal(tag, sig_b);
auto tag_sig_s = tag_signal(tag, sig_s);
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, prop_a);
tag_sig_b = autoAnd(NEW_ID, tag_sig_b, prop_b);
tag_sig_s = autoAnd(NEW_ID, tag_sig_s, prop_s);
tag_sig_a = autoAnd(NEWER_ID, tag_sig_a, prop_a);
tag_sig_b = autoAnd(NEWER_ID, tag_sig_b, prop_b);
tag_sig_s = autoAnd(NEWER_ID, tag_sig_s, prop_s);
auto tag_sig = autoOr(NEW_ID, tag_sig_s,
autoOr(NEW_ID, tag_sig_a, tag_sig_b));
auto tag_sig = autoOr(NEWER_ID, tag_sig_s,
autoOr(NEWER_ID, tag_sig_a, tag_sig_b));
emit_tag_signal(tag, sig_y, tag_sig);
return;
}
@ -620,15 +620,15 @@ struct DftTagWorker {
auto tag_sig_a = tag_signal(tag, sig_a);
auto tag_sig_b = tag_signal(tag, sig_b);
auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b);
auto group_sig = autoOr(NEWER_ID, group_sig_a, group_sig_b);
// The output can only be affected by the tagged inputs if all group-untagged bits are equal
auto masked_a = autoOr(NEW_ID, sig_a, group_sig);
auto masked_b = autoOr(NEW_ID, sig_b, group_sig);
auto masked_a = autoOr(NEWER_ID, sig_a, group_sig);
auto masked_b = autoOr(NEWER_ID, sig_b, group_sig);
auto prop = autoEq(NEW_ID, masked_a, masked_b);
auto prop = autoEq(NEWER_ID, masked_a, masked_b);
auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b}));
auto tag_sig = autoAnd(NEWER_ID, prop, autoReduceOr(NEWER_ID, {tag_sig_a, tag_sig_b}));
tag_sig.extend_u0(GetSize(sig_y), false);
emit_tag_signal(tag, sig_y, tag_sig);
return;
@ -652,15 +652,15 @@ struct DftTagWorker {
auto tag_sig_a = tag_signal(tag, sig_a);
auto tag_sig_b = tag_signal(tag, sig_b);
auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b);
auto group_sig = autoOr(NEWER_ID, group_sig_a, group_sig_b);
// The output can only be affected by the tagged inputs if the greatest possible sig_a is
// greater or equal to the least possible sig_b
auto masked_a = autoOr(NEW_ID, sig_a, group_sig);
auto masked_b = autoAnd(NEW_ID, sig_b, autoNot(NEW_ID, group_sig));
auto masked_a = autoOr(NEWER_ID, sig_a, group_sig);
auto masked_b = autoAnd(NEWER_ID, sig_b, autoNot(NEWER_ID, group_sig));
auto prop = autoGe(NEW_ID, masked_a, masked_b);
auto prop = autoGe(NEWER_ID, masked_a, masked_b);
auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b}));
auto tag_sig = autoAnd(NEWER_ID, prop, autoReduceOr(NEWER_ID, {tag_sig_a, tag_sig_b}));
tag_sig.extend_u0(GetSize(sig_y), false);
emit_tag_signal(tag, sig_y, tag_sig);
return;
@ -674,13 +674,13 @@ struct DftTagWorker {
auto tag_sig_a = tag_signal(tag, sig_a);
if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not)))
sig_a = autoNot(NEW_ID, sig_a);
sig_a = autoNot(NEWER_ID, sig_a);
auto filled = autoOr(NEW_ID, sig_a, group_sig_a);
auto filled = autoOr(NEWER_ID, sig_a, group_sig_a);
auto prop = autoReduceAnd(NEW_ID, filled);
auto tagged = autoReduceOr(NEW_ID, tag_sig_a);
auto tag_sig = autoAnd(NEW_ID, prop, tagged);
auto prop = autoReduceAnd(NEWER_ID, filled);
auto tagged = autoReduceOr(NEWER_ID, tag_sig_a);
auto tag_sig = autoAnd(NEWER_ID, prop, tagged);
tag_sig.extend_u0(GetSize(sig_y), false);
emit_tag_signal(tag, sig_y, tag_sig);
return;
@ -698,10 +698,10 @@ struct DftTagWorker {
auto sig_q = ff.sig_q;
auto sig_d = ff.sig_d;
ff.name = NEW_ID;
ff.name = NEWER_ID;
ff.cell = nullptr;
ff.sig_d = tag_signal(tag, ff.sig_d);
ff.sig_q = module->addWire(NEW_ID, width);
ff.sig_q = module->addWire(NEWER_ID, width);
ff.is_anyinit = false;
ff.val_init = Const(0, width);
ff.emit();
@ -727,7 +727,7 @@ struct DftTagWorker {
}
}
SigBit any_tagged = autoReduceOr(NEW_ID, tag_input);
SigBit any_tagged = autoReduceOr(NEWER_ID, tag_input);
for (auto &conn : cell->connections()) {
if (cell->output(conn.first)) {

2
passes/cmds/glift.cc
View file

@ -144,7 +144,7 @@ private:
//In this case, a nonzero hole metamux select value means less logic.
//Thus we should invert the ReduceOr over the metamux_select signal.
RTLIL::SigSpec pmux_select = module->ReduceOr(metamux_select.as_wire()->name.str() + "_nonzero", metamux_select);
return module->Pmux(NEW_ID, RTLIL::Const(1), RTLIL::Const(0), pmux_select, metamux_select.as_wire()->get_src_attribute());
return module->Pmux(NEWER_ID, RTLIL::Const(1), RTLIL::Const(0), pmux_select, metamux_select.as_wire()->get_src_attribute());
} else {
auto select_width = metamux_select.as_wire()->width;

2
passes/cmds/portarcs.cc
View file

@ -291,7 +291,7 @@ struct PortarcsPass : Pass {
int *p = annotations.at(canonical_bit(bit));
for (auto i = 0; i < inputs.size(); i++) {
if (p[i] >= 0) {
Cell *spec = m->addCell(NEW_ID, ID($specify2));
Cell *spec = m->addCell(NEWER_ID, ID($specify2));
spec->setParam(ID::SRC_WIDTH, 1);
spec->setParam(ID::DST_WIDTH, 1);
spec->setParam(ID::T_FALL_MAX, p[i]);

4
passes/cmds/rename.cc
View file

@ -494,11 +494,11 @@ struct RenamePass : public Pass {
for (auto wire : module->selected_wires())
if (wire->name.isPublic() && wire->port_id == 0)
new_wire_names[wire] = NEW_ID;
new_wire_names[wire] = NEWER_ID;
for (auto cell : module->selected_cells())
if (cell->name.isPublic())
new_cell_names[cell] = NEW_ID;
new_cell_names[cell] = NEWER_ID;
for (auto &it : new_wire_names)
module->rename(it.first, it.second);

2
passes/cmds/scatter.cc
View file

@ -51,7 +51,7 @@ struct ScatterPass : public Pass {
for (auto cell : module->cells()) {
dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
for (auto conn : cell->connections())
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEWER_ID, GetSize(conn.second))));
for (auto &it : new_connections) {
if (ct.cell_output(cell->type, it.first))
module->connect(RTLIL::SigSig(it.second.first, it.second.second));

8
passes/cmds/setundef.cc
View file

@ -345,9 +345,9 @@ struct SetundefPass : public Pass {
for (auto &c : sig.chunks()) {
RTLIL::SigSpec bits;
if (worker.next_bit_mode == MODE_ANYSEQ)
bits = module->Anyseq(NEW_ID, c.width);
bits = module->Anyseq(NEWER_ID, c.width);
else if (worker.next_bit_mode == MODE_ANYCONST)
bits = module->Anyconst(NEW_ID, c.width);
bits = module->Anyconst(NEWER_ID, c.width);
else
for (int i = 0; i < c.width; i++)
bits.append(worker.next_bit());
@ -530,9 +530,9 @@ struct SetundefPass : public Pass {
if (width > 0) {
if (worker.next_bit_mode == MODE_ANYSEQ)
sig.replace(cursor, module->Anyseq(NEW_ID, width));
sig.replace(cursor, module->Anyseq(NEWER_ID, width));
else
sig.replace(cursor, module->Anyconst(NEW_ID, width));
sig.replace(cursor, module->Anyconst(NEWER_ID, width));
cursor += width;
} else {
cursor++;

10
passes/cmds/splice.cc
View file

@ -75,12 +75,12 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($slice));
cell->parameters[ID::OFFSET] = offset;
cell->parameters[ID::A_WIDTH] = sig_a.size();
cell->parameters[ID::Y_WIDTH] = sig.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
cell->setPort(ID::Y, module->addWire(NEWER_ID, sig.size()));
new_sig = cell->getPort(ID::Y);
}
@ -132,12 +132,12 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($concat));
cell->parameters[ID::A_WIDTH] = new_sig.size();
cell->parameters[ID::B_WIDTH] = sig2.size();
cell->setPort(ID::A, new_sig);
cell->setPort(ID::B, sig2);
cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));
cell->setPort(ID::Y, module->addWire(NEWER_ID, new_sig.size() + sig2.size()));
new_sig = cell->getPort(ID::Y);
}
@ -232,7 +232,7 @@ struct SpliceWorker
for (auto &it : rework_wires)
{
RTLIL::IdString orig_name = it.first->name;
module->rename(it.first, NEW_ID);
module->rename(it.first, NEWER_ID);
RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
it.first->port_id = 0;

178
passes/cmds/xprop.cc
View file

@ -55,18 +55,18 @@ struct XpropWorker
Module *module;
void invert() { std::swap(is_0, is_1); }
void auto_0() { connect_0(module->Not(NEW_ID, module->Or(NEW_ID, is_1, is_x))); }
void auto_1() { connect_1(module->Not(NEW_ID, module->Or(NEW_ID, is_0, is_x))); }
void auto_x() { connect_x(module->Not(NEW_ID, module->Or(NEW_ID, is_0, is_1))); }
void auto_0() { connect_0(module->Not(NEWER_ID, module->Or(NEWER_ID, is_1, is_x))); }
void auto_1() { connect_1(module->Not(NEWER_ID, module->Or(NEWER_ID, is_0, is_x))); }
void auto_x() { connect_x(module->Not(NEWER_ID, module->Or(NEWER_ID, is_0, is_1))); }
void connect_0(SigSpec sig) { module->connect(is_0, sig); }
void connect_1(SigSpec sig) { module->connect(is_1, sig); }
void connect_x(SigSpec sig) { module->connect(is_x, sig); }
void connect_1_under_x(SigSpec sig) { connect_1(module->And(NEW_ID, sig, module->Not(NEW_ID, is_x))); }
void connect_0_under_x(SigSpec sig) { connect_0(module->And(NEW_ID, sig, module->Not(NEW_ID, is_x))); }
void connect_1_under_x(SigSpec sig) { connect_1(module->And(NEWER_ID, sig, module->Not(NEWER_ID, is_x))); }
void connect_0_under_x(SigSpec sig) { connect_0(module->And(NEWER_ID, sig, module->Not(NEWER_ID, is_x))); }
void connect_x_under_0(SigSpec sig) { connect_x(module->And(NEW_ID, sig, module->Not(NEW_ID, is_0))); }
void connect_x_under_0(SigSpec sig) { connect_x(module->And(NEWER_ID, sig, module->Not(NEWER_ID, is_0))); }
void connect_as_bool() {
int width = GetSize(is_0);
@ -198,13 +198,13 @@ struct XpropWorker
}
if (!invert.empty() && !driving)
invert = module->Not(NEW_ID, invert);
invert = module->Not(NEWER_ID, invert);
EncodedSig new_sigs;
if (new_bits > 0) {
new_sigs.is_0 = module->addWire(NEW_ID, new_bits);
new_sigs.is_1 = module->addWire(NEW_ID, new_bits);
new_sigs.is_x = module->addWire(NEW_ID, new_bits);
new_sigs.is_0 = module->addWire(NEWER_ID, new_bits);
new_sigs.is_1 = module->addWire(NEWER_ID, new_bits);
new_sigs.is_x = module->addWire(NEWER_ID, new_bits);
}
int invert_pos = 0;
@ -253,7 +253,7 @@ struct XpropWorker
}
if (!driven_orig.empty()) {
auto decoder = module->addBwmux(NEW_ID, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig);
auto decoder = module->addBwmux(NEWER_ID, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig);
decoder->set_bool_attribute(ID::xprop_decoder);
}
if (!driven_never_x.first.empty()) {
@ -261,21 +261,21 @@ struct XpropWorker
}
if (driving && (options.assert_encoding || options.assume_encoding)) {
auto not_0 = module->Not(NEW_ID, result.is_0);
auto not_1 = module->Not(NEW_ID, result.is_1);
auto not_x = module->Not(NEW_ID, result.is_x);
auto valid = module->ReduceAnd(NEW_ID, {
module->Eq(NEW_ID, result.is_0, module->And(NEW_ID, not_1, not_x)),
module->Eq(NEW_ID, result.is_1, module->And(NEW_ID, not_0, not_x)),
module->Eq(NEW_ID, result.is_x, module->And(NEW_ID, not_0, not_1)),
auto not_0 = module->Not(NEWER_ID, result.is_0);
auto not_1 = module->Not(NEWER_ID, result.is_1);
auto not_x = module->Not(NEWER_ID, result.is_x);
auto valid = module->ReduceAnd(NEWER_ID, {
module->Eq(NEWER_ID, result.is_0, module->And(NEWER_ID, not_1, not_x)),
module->Eq(NEWER_ID, result.is_1, module->And(NEWER_ID, not_0, not_x)),
module->Eq(NEWER_ID, result.is_x, module->And(NEWER_ID, not_0, not_1)),
});
if (options.assert_encoding)
module->addAssert(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1);
module->addAssert(NEWER_ID_SUFFIX("xprop_enc"), valid, State::S1);
else
module->addAssume(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1);
module->addAssume(NEWER_ID_SUFFIX("xprop_enc"), valid, State::S1);
if (options.debug_asserts) {
auto bad_bits = module->Bweqx(NEW_ID, {result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3));
module->addAssert(NEW_ID_SUFFIX("xprop_debug"), module->LogicNot(NEW_ID, bad_bits), State::S1);
auto bad_bits = module->Bweqx(NEWER_ID, {result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3));
module->addAssert(NEWER_ID_SUFFIX("xprop_debug"), module->LogicNot(NEWER_ID, bad_bits), State::S1);
}
}
@ -543,8 +543,8 @@ struct XpropWorker
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
enc_b.invert();
enc_y.connect_0(module->Or(NEW_ID, enc_a.is_0, enc_b.is_0));
enc_y.connect_1(module->And(NEW_ID, enc_a.is_1, enc_b.is_1));
enc_y.connect_0(module->Or(NEWER_ID, enc_a.is_0, enc_b.is_0));
enc_y.connect_1(module->And(NEWER_ID, enc_a.is_1, enc_b.is_1));
enc_y.auto_x();
module->remove(cell);
return;
@ -564,8 +564,8 @@ struct XpropWorker
if (cell->type == ID($logic_not))
enc_a.invert();
enc_y.connect_0(module->ReduceOr(NEW_ID, enc_a.is_0));
enc_y.connect_1(module->ReduceAnd(NEW_ID, enc_a.is_1));
enc_y.connect_0(module->ReduceOr(NEWER_ID, enc_a.is_0));
enc_y.connect_1(module->ReduceAnd(NEWER_ID, enc_a.is_1));
enc_y.auto_x();
module->remove(cell);
@ -584,8 +584,8 @@ struct XpropWorker
enc_y.invert();
enc_y.connect_x(module->ReduceOr(NEW_ID, enc_a.is_x));
enc_y.connect_1_under_x(module->ReduceXor(NEW_ID, enc_a.is_1));
enc_y.connect_x(module->ReduceOr(NEWER_ID, enc_a.is_x));
enc_y.connect_1_under_x(module->ReduceXor(NEWER_ID, enc_a.is_1));
enc_y.auto_0();
module->remove(cell);
@ -603,16 +603,16 @@ struct XpropWorker
enc_y.connect_as_bool();
auto a_is_1 = module->ReduceOr(NEW_ID, enc_a.is_1);
auto a_is_0 = module->ReduceAnd(NEW_ID, enc_a.is_0);
auto b_is_1 = module->ReduceOr(NEW_ID, enc_b.is_1);
auto b_is_0 = module->ReduceAnd(NEW_ID, enc_b.is_0);
auto a_is_1 = module->ReduceOr(NEWER_ID, enc_a.is_1);
auto a_is_0 = module->ReduceAnd(NEWER_ID, enc_a.is_0);
auto b_is_1 = module->ReduceOr(NEWER_ID, enc_b.is_1);
auto b_is_0 = module->ReduceAnd(NEWER_ID, enc_b.is_0);
if (cell->type == ID($logic_or))
enc_y.invert(), std::swap(a_is_0, a_is_1), std::swap(b_is_0, b_is_1);
enc_y.connect_0(module->Or(NEW_ID, a_is_0, b_is_0));
enc_y.connect_1(module->And(NEW_ID, a_is_1, b_is_1));
enc_y.connect_0(module->Or(NEWER_ID, a_is_0, b_is_0));
enc_y.connect_1(module->And(NEWER_ID, a_is_1, b_is_1));
enc_y.auto_x();
module->remove(cell);
return;
@ -634,8 +634,8 @@ struct XpropWorker
if (cell->type.in(ID($xnor), ID($_XNOR_)))
enc_y.invert();
enc_y.connect_x(module->Or(NEW_ID, enc_a.is_x, enc_b.is_x));
enc_y.connect_1_under_x(module->Xor(NEW_ID, enc_a.is_1, enc_b.is_1));
enc_y.connect_x(module->Or(NEWER_ID, enc_a.is_x, enc_b.is_x));
enc_y.connect_1_under_x(module->Xor(NEWER_ID, enc_a.is_1, enc_b.is_1));
enc_y.auto_0();
module->remove(cell);
return;
@ -657,11 +657,11 @@ struct XpropWorker
if (cell->type == ID($ne))
enc_y.invert();
auto delta = module->Xor(NEW_ID, enc_a.is_1, enc_b.is_1);
auto xpos = module->Or(NEW_ID, enc_a.is_x, enc_b.is_x);
auto delta = module->Xor(NEWER_ID, enc_a.is_1, enc_b.is_1);
auto xpos = module->Or(NEWER_ID, enc_a.is_x, enc_b.is_x);
enc_y.connect_0(module->ReduceOr(NEW_ID, module->And(NEW_ID, delta, module->Not(NEW_ID, xpos))));
enc_y.connect_x_under_0(module->ReduceOr(NEW_ID, xpos));
enc_y.connect_0(module->ReduceOr(NEWER_ID, module->And(NEWER_ID, delta, module->Not(NEWER_ID, xpos))));
enc_y.connect_x_under_0(module->ReduceOr(NEWER_ID, xpos));
enc_y.auto_1();
module->remove(cell);
return;
@ -678,12 +678,12 @@ struct XpropWorker
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0);
auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1);
auto delta_0 = module->Xnor(NEWER_ID, enc_a.is_0, enc_b.is_0);
auto delta_1 = module->Xnor(NEWER_ID, enc_a.is_1, enc_b.is_1);
auto eq = module->ReduceAnd(NEW_ID, {delta_0, delta_1});
auto eq = module->ReduceAnd(NEWER_ID, {delta_0, delta_1});
auto res = cell->type == ID($nex) ? module->Not(NEW_ID, eq) : eq;
auto res = cell->type == ID($nex) ? module->Not(NEWER_ID, eq) : eq;
module->connect(sig_y[0], res);
if (GetSize(sig_y) > 1)
@ -700,9 +700,9 @@ struct XpropWorker
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0);
auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1);
module->addAnd(NEW_ID, delta_0, delta_1, sig_y);
auto delta_0 = module->Xnor(NEWER_ID, enc_a.is_0, enc_b.is_0);
auto delta_1 = module->Xnor(NEWER_ID, enc_a.is_1, enc_b.is_1);
module->addAnd(NEWER_ID, delta_0, delta_1, sig_y);
module->remove(cell);
return;
}
@ -721,12 +721,12 @@ struct XpropWorker
auto enc_s = encoded(sig_s);
auto enc_y = encoded(sig_y, true);
enc_y.connect_1(module->And(NEW_ID,
module->Or(NEW_ID, enc_a.is_1, enc_s.is_1),
module->Or(NEW_ID, enc_b.is_1, enc_s.is_0)));
enc_y.connect_0(module->And(NEW_ID,
module->Or(NEW_ID, enc_a.is_0, enc_s.is_1),
module->Or(NEW_ID, enc_b.is_0, enc_s.is_0)));
enc_y.connect_1(module->And(NEWER_ID,
module->Or(NEWER_ID, enc_a.is_1, enc_s.is_1),
module->Or(NEWER_ID, enc_b.is_1, enc_s.is_0)));
enc_y.connect_0(module->And(NEWER_ID,
module->Or(NEWER_ID, enc_a.is_0, enc_s.is_1),
module->Or(NEWER_ID, enc_b.is_0, enc_s.is_0)));
enc_y.auto_x();
module->remove(cell);
return;
@ -745,23 +745,23 @@ struct XpropWorker
int width = GetSize(enc_y);
auto all_x = module->ReduceOr(NEW_ID, {
auto all_x = module->ReduceOr(NEWER_ID, {
enc_s.is_x,
module->And(NEW_ID, enc_s.is_1, module->Sub(NEW_ID, enc_s.is_1, Const(1, width)))
module->And(NEWER_ID, enc_s.is_1, module->Sub(NEWER_ID, enc_s.is_1, Const(1, width)))
});
auto selected = enc_a;
for (int i = 0; i < GetSize(enc_s); i++) {
auto sel_bit = enc_s.is_1[i];
selected.is_0 = module->Mux(NEW_ID, selected.is_0, enc_b.is_0.extract(i * width, width), sel_bit);
selected.is_1 = module->Mux(NEW_ID, selected.is_1, enc_b.is_1.extract(i * width, width), sel_bit);
selected.is_x = module->Mux(NEW_ID, selected.is_x, enc_b.is_x.extract(i * width, width), sel_bit);
selected.is_0 = module->Mux(NEWER_ID, selected.is_0, enc_b.is_0.extract(i * width, width), sel_bit);
selected.is_1 = module->Mux(NEWER_ID, selected.is_1, enc_b.is_1.extract(i * width, width), sel_bit);
selected.is_x = module->Mux(NEWER_ID, selected.is_x, enc_b.is_x.extract(i * width, width), sel_bit);
}
enc_y.connect_0(module->Mux(NEW_ID, selected.is_0, Const(State::S0, width), all_x));
enc_y.connect_1(module->Mux(NEW_ID, selected.is_1, Const(State::S0, width), all_x));
enc_y.connect_x(module->Mux(NEW_ID, selected.is_x, Const(State::S1, width), all_x));
enc_y.connect_0(module->Mux(NEWER_ID, selected.is_0, Const(State::S0, width), all_x));
enc_y.connect_1(module->Mux(NEWER_ID, selected.is_1, Const(State::S0, width), all_x));
enc_y.connect_x(module->Mux(NEWER_ID, selected.is_x, Const(State::S1, width), all_x));
module->remove(cell);
return;
@ -776,12 +776,12 @@ struct XpropWorker
auto enc_b = encoded(sig_b);
auto enc_y = encoded(sig_y, true);
auto all_x = module->ReduceOr(NEW_ID, enc_b.is_x)[0];
auto not_all_x = module->Not(NEW_ID, all_x)[0];
auto all_x = module->ReduceOr(NEWER_ID, enc_b.is_x)[0];
auto not_all_x = module->Not(NEWER_ID, all_x)[0];
SigSpec y_not_0 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_1 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_x = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_not_0 = module->addWire(NEWER_ID, GetSize(sig_y));
SigSpec y_1 = module->addWire(NEWER_ID, GetSize(sig_y));
SigSpec y_x = module->addWire(NEWER_ID, GetSize(sig_y));
auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
@ -789,32 +789,32 @@ struct XpropWorker
std::swap(enc_a.is_0, enc_a.is_x);
}
auto shift_0 = module->addCell(NEW_ID, encoded_type);
auto shift_0 = module->addCell(NEWER_ID, encoded_type);
shift_0->parameters = cell->parameters;
shift_0->setPort(ID::A, module->Not(NEW_ID, enc_a.is_0));
shift_0->setPort(ID::A, module->Not(NEWER_ID, enc_a.is_0));
shift_0->setPort(ID::B, enc_b.is_1);
shift_0->setPort(ID::Y, y_not_0);
auto shift_1 = module->addCell(NEW_ID, encoded_type);
auto shift_1 = module->addCell(NEWER_ID, encoded_type);
shift_1->parameters = cell->parameters;
shift_1->setPort(ID::A, enc_a.is_1);
shift_1->setPort(ID::B, enc_b.is_1);
shift_1->setPort(ID::Y, y_1);
auto shift_x = module->addCell(NEW_ID, encoded_type);
auto shift_x = module->addCell(NEWER_ID, encoded_type);
shift_x->parameters = cell->parameters;
shift_x->setPort(ID::A, enc_a.is_x);
shift_x->setPort(ID::B, enc_b.is_1);
shift_x->setPort(ID::Y, y_x);
SigSpec y_0 = module->Not(NEW_ID, y_not_0);
SigSpec y_0 = module->Not(NEWER_ID, y_not_0);
if (cell->type == ID($shiftx))
std::swap(y_0, y_x);
enc_y.connect_0(module->And(NEW_ID, y_0, SigSpec(not_all_x, GetSize(sig_y))));
enc_y.connect_1(module->And(NEW_ID, y_1, SigSpec(not_all_x, GetSize(sig_y))));
enc_y.connect_x(module->Or(NEW_ID, y_x, SigSpec(all_x, GetSize(sig_y))));
enc_y.connect_0(module->And(NEWER_ID, y_0, SigSpec(not_all_x, GetSize(sig_y))));
enc_y.connect_1(module->And(NEWER_ID, y_1, SigSpec(not_all_x, GetSize(sig_y))));
enc_y.connect_x(module->Or(NEWER_ID, y_x, SigSpec(all_x, GetSize(sig_y))));
module->remove(cell);
return;
@ -838,10 +838,10 @@ struct XpropWorker
auto enc_d = encoded(sig_d);
auto enc_q = encoded(sig_q, true);
auto data_q = module->addWire(NEW_ID, GetSize(sig_q));
auto data_q = module->addWire(NEWER_ID, GetSize(sig_q));
module->addFf(NEW_ID, enc_d.is_1, data_q);
module->addFf(NEW_ID, enc_d.is_x, enc_q.is_x);
module->addFf(NEWER_ID, enc_d.is_1, data_q);
module->addFf(NEWER_ID, enc_d.is_x, enc_q.is_x);
initvals.set_init(data_q, init_q_is_1);
initvals.set_init(enc_q.is_x, init_q_is_x);
@ -881,14 +881,14 @@ struct XpropWorker
auto enc_d = encoded(ff.sig_d);
auto enc_q = encoded(ff.sig_q, true);
auto data_q = module->addWire(NEW_ID, GetSize(ff.sig_q));
auto data_q = module->addWire(NEWER_ID, GetSize(ff.sig_q));
ff.sig_d = enc_d.is_1;
ff.sig_q = data_q;
ff.val_init = init_q_is_1;
ff.emit();
ff.name = NEW_ID;
ff.name = NEWER_ID;
ff.cell = nullptr;
ff.sig_d = enc_d.is_x;
ff.sig_q = enc_q.is_x;
@ -925,13 +925,13 @@ struct XpropWorker
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
auto sig_b = cell->getPort(ID::B);
auto invalid = module->LogicNot(NEW_ID, sig_b);
auto invalid = module->LogicNot(NEWER_ID, sig_b);
inbits_x.append(invalid);
sig_b[0] = module->Or(NEW_ID, sig_b[0], invalid);
sig_b[0] = module->Or(NEWER_ID, sig_b[0], invalid);
cell->setPort(ID::B, sig_b);
}
SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_ID, inbits_x));
SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEWER_ID, inbits_x));
bool bool_out = cell->type.in(ID($le), ID($lt), ID($ge), ID($gt));
@ -941,7 +941,7 @@ struct XpropWorker
if (bool_out)
enc_port.connect_as_bool();
SigSpec new_output = module->addWire(NEW_ID, GetSize(conn.second));
SigSpec new_output = module->addWire(NEWER_ID, GetSize(conn.second));
enc_port.connect_1_under_x(bool_out ? new_output.extract(0) : new_output);
enc_port.connect_x(SigSpec(outbits_x, GetSize(enc_port)));
@ -999,7 +999,7 @@ struct XpropWorker
if (options.split_public) {
// Need to hide the original wire so split_public doesn't try to split it again
module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
module->rename(wire, NEWER_ID_SUFFIX(wire->name.c_str()));
}
} else {
auto enc = encoded(wire, true);
@ -1052,7 +1052,7 @@ struct XpropWorker
module->connect(wire_d, enc.is_1);
module->connect(wire_x, enc.is_x);
module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
module->rename(wire, NEWER_ID_SUFFIX(wire->name.c_str()));
}
}
@ -1092,9 +1092,9 @@ struct XpropWorker
it->second.driven = true;
}
module->addBweqx(NEW_ID, orig, Const(State::S0, GetSize(orig)), enc.is_0);
module->addBweqx(NEW_ID, orig, Const(State::S1, GetSize(orig)), enc.is_1);
module->addBweqx(NEW_ID, orig, Const(State::Sx, GetSize(orig)), enc.is_x);
module->addBweqx(NEWER_ID, orig, Const(State::S0, GetSize(orig)), enc.is_0);
module->addBweqx(NEWER_ID, orig, Const(State::S1, GetSize(orig)), enc.is_1);
module->addBweqx(NEWER_ID, orig, Const(State::Sx, GetSize(orig)), enc.is_x);
}
}
};
@ -1230,7 +1230,7 @@ struct XpropPass : public Pass {
continue;
if (wire->port_input) {
module->addAssume(NEW_ID, module->Not(NEW_ID, module->ReduceOr(NEW_ID, module->Bweqx(NEW_ID, wire, Const(State::Sx, GetSize(wire))))), State::S1);
module->addAssume(NEWER_ID, module->Not(NEWER_ID, module->ReduceOr(NEWER_ID, module->Bweqx(NEWER_ID, wire, Const(State::Sx, GetSize(wire))))), State::S1);
}
}
}

14
passes/equiv/equiv_add.cc
View file

@ -84,10 +84,10 @@ struct EquivAddPass : public Pass {
if (gold_cell->input(port) && gate_cell->input(port))
{
SigSpec combined_sig = module->addWire(NEW_ID, width);
SigSpec combined_sig = module->addWire(NEWER_ID, width);
for (int i = 0; i < width; i++) {
module->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], combined_sig[i]);
module->addEquiv(NEWER_ID, gold_sig[i], gate_sig[i], combined_sig[i]);
gold_sig[i] = gate_sig[i] = combined_sig[i];
}
@ -98,12 +98,12 @@ struct EquivAddPass : public Pass {
if (gold_cell->output(port) && gate_cell->output(port))
{
SigSpec new_gold_wire = module->addWire(NEW_ID, width);
SigSpec new_gate_wire = module->addWire(NEW_ID, width);
SigSpec new_gold_wire = module->addWire(NEWER_ID, width);
SigSpec new_gate_wire = module->addWire(NEWER_ID, width);
SigSig gg_conn;
for (int i = 0; i < width; i++) {
module->addEquiv(NEW_ID, new_gold_wire[i], new_gold_wire[i], gold_sig[i]);
module->addEquiv(NEWER_ID, new_gold_wire[i], new_gold_wire[i], gold_sig[i]);
gg_conn.first.append(gate_sig[i]);
gg_conn.second.append(gold_sig[i]);
gold_sig[i] = new_gold_wire[i];
@ -141,7 +141,7 @@ struct EquivAddPass : public Pass {
}
log_assert(GetSize(gold_signal) == GetSize(gate_signal));
SigSpec equiv_signal = module->addWire(NEW_ID, GetSize(gold_signal));
SigSpec equiv_signal = module->addWire(NEWER_ID, GetSize(gold_signal));
SigMap sigmap(module);
sigmap.apply(gold_signal);
@ -151,7 +151,7 @@ struct EquivAddPass : public Pass {
pool<Cell*> added_equiv_cells;
for (int i = 0; i < GetSize(gold_signal); i++) {
Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
Cell *equiv_cell = module->addEquiv(NEWER_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
equiv_cell->set_bool_attribute(ID::keep);
to_equiv_bits[gold_signal[i]] = equiv_signal[i];
to_equiv_bits[gate_signal[i]] = equiv_signal[i];

24
passes/equiv/equiv_make.cc
View file

@ -136,8 +136,8 @@ struct EquivMakeWorker
void add_eq_assertion(const SigSpec &gold_sig, const SigSpec &gate_sig)
{
auto eq_wire = equiv_mod->Eqx(NEW_ID, gold_sig, gate_sig);
equiv_mod->addAssert(NEW_ID_SUFFIX("assert"), eq_wire, State::S1);
auto eq_wire = equiv_mod->Eqx(NEWER_ID, gold_sig, gate_sig);
equiv_mod->addAssert(NEWER_ID_SUFFIX("assert"), eq_wire, State::S1);
}
void find_same_wires()
@ -205,11 +205,11 @@ struct EquivMakeWorker
for (auto &bit : enc_result)
if (bit != State::S1) bit = State::S0;
SigSpec dec_eq = equiv_mod->addWire(NEW_ID);
SigSpec enc_eq = equiv_mod->addWire(NEW_ID);
SigSpec dec_eq = equiv_mod->addWire(NEWER_ID);
SigSpec enc_eq = equiv_mod->addWire(NEWER_ID);
equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq);
cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq));
equiv_mod->addEq(NEWER_ID, reduced_dec_sig, reduced_dec_pat, dec_eq);
cells_list.push_back(equiv_mod->addEq(NEWER_ID, reduced_enc_sig, reduced_enc_pat, enc_eq));
dec_s.append(dec_eq);
enc_s.append(enc_eq);
@ -217,8 +217,8 @@ struct EquivMakeWorker
enc_b.append(enc_result);
}
equiv_mod->addPmux(NEW_ID, dec_a, dec_b, dec_s, dec_wire);
equiv_mod->addPmux(NEW_ID, enc_a, enc_b, enc_s, enc_wire);
equiv_mod->addPmux(NEWER_ID, dec_a, dec_b, dec_s, dec_wire);
equiv_mod->addPmux(NEWER_ID, enc_a, enc_b, enc_s, enc_wire);
rd_signal_map.add(assign_map(gate_wire), enc_wire);
gate_wire = dec_wire;
@ -254,7 +254,7 @@ struct EquivMakeWorker
else
{
for (int i = 0; i < wire->width; i++)
equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
equiv_mod->addEquiv(NEWER_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
}
rd_signal_map.add(assign_map(gold_wire), wire);
@ -291,7 +291,7 @@ struct EquivMakeWorker
log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i);
continue;
}
equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
equiv_mod->addEquiv(NEWER_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
rdmap_gold.append(SigBit(gold_wire, i));
rdmap_gate.append(SigBit(gate_wire, i));
rdmap_equiv.append(SigBit(wire, i));
@ -365,8 +365,8 @@ struct EquivMakeWorker
{
for (int i = 0; i < GetSize(gold_sig); i++)
if (gold_sig[i] != gate_sig[i]) {
Wire *w = equiv_mod->addWire(NEW_ID);
equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w);
Wire *w = equiv_mod->addWire(NEWER_ID);
equiv_mod->addEquiv(NEWER_ID, gold_sig[i], gate_sig[i], w);
gold_sig[i] = w;
}
}

12
passes/equiv/equiv_miter.cc
View file

@ -219,9 +219,9 @@ struct EquivMiterWorker
for (auto c : equiv_cells)
{
SigSpec cmp = mode_undef ?
miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx),
miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) :
miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B));
miter_module->LogicOr(NEWER_ID, miter_module->Eqx(NEWER_ID, c->getPort(ID::A), State::Sx),
miter_module->Eqx(NEWER_ID, c->getPort(ID::A), c->getPort(ID::B))) :
miter_module->Eq(NEWER_ID, c->getPort(ID::A), c->getPort(ID::B));
if (mode_cmp) {
string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y)));
@ -236,15 +236,15 @@ struct EquivMiterWorker
}
if (mode_assert)
miter_module->addAssert(NEW_ID, cmp, State::S1);
miter_module->addAssert(NEWER_ID, cmp, State::S1);
trigger_signals.append(miter_module->Not(NEW_ID, cmp));
trigger_signals.append(miter_module->Not(NEWER_ID, cmp));
}
if (mode_trigger) {
auto w = miter_module->addWire(ID(trigger));
w->port_output = true;
miter_module->addReduceOr(NEW_ID, trigger_signals, w);
miter_module->addReduceOr(NEWER_ID, trigger_signals, w);
}
miter_module->fixup_ports();

4
passes/equiv/equiv_purge.cc
View file

@ -67,7 +67,7 @@ struct EquivPurgeWorker
log(" Module input: %s\n", log_signal(wire));
wire->port_input = true;
}
return module->addWire(NEW_ID, GetSize(sig));
return module->addWire(NEWER_ID, GetSize(sig));
}
}
@ -81,7 +81,7 @@ struct EquivPurgeWorker
wire->port_input = true;
module->connect(sig, wire);
log(" Module input: %s (%s)\n", log_signal(wire), log_signal(sig));
return module->addWire(NEW_ID, GetSize(sig));
return module->addWire(NEWER_ID, GetSize(sig));
}
}

4
passes/equiv/equiv_struct.cc
View file

@ -85,10 +85,10 @@ struct EquivStructWorker
for (int i = 0; i < GetSize(inputs_a); i++) {
SigBit bit_a = inputs_a[i], bit_b = inputs_b[i];
SigBit bit_y = module->addWire(NEW_ID);
SigBit bit_y = module->addWire(NEWER_ID);
log(" New $equiv for input %s: A: %s, B: %s, Y: %s\n",
input_names[i].c_str(), log_signal(bit_a), log_signal(bit_b), log_signal(bit_y));
module->addEquiv(NEW_ID, bit_a, bit_b, bit_y);
module->addEquiv(NEWER_ID, bit_a, bit_b, bit_y);
merged_map.add(bit_a, bit_y);
merged_map.add(bit_b, bit_y);
}

26
passes/fsm/fsm_map.cc
View file

@ -71,10 +71,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
if (eq_sig_a.size() > 0)
{
RTLIL::Wire *eq_wire = module->addWire(NEW_ID);
RTLIL::Wire *eq_wire = module->addWire(NEWER_ID);
and_sig.append(RTLIL::SigSpec(eq_wire));
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
RTLIL::Cell *eq_cell = module->addCell(NEWER_ID, ID($eq));
eq_cell->setPort(ID::A, eq_sig_a);
eq_cell->setPort(ID::B, eq_sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire));
@ -99,10 +99,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
}
else
{
RTLIL::Wire *or_wire = module->addWire(NEW_ID);
RTLIL::Wire *or_wire = module->addWire(NEWER_ID);
and_sig.append(RTLIL::SigSpec(or_wire));
RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
RTLIL::Cell *or_cell = module->addCell(NEWER_ID, ID($reduce_or));
or_cell->setPort(ID::A, or_sig);
or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire));
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
@ -115,10 +115,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
{
case 2:
{
RTLIL::Wire *and_wire = module->addWire(NEW_ID);
RTLIL::Wire *and_wire = module->addWire(NEWER_ID);
cases_vector.append(RTLIL::SigSpec(and_wire));
RTLIL::Cell *and_cell = module->addCell(NEW_ID, ID($and));
RTLIL::Cell *and_cell = module->addCell(NEWER_ID, ID($and));
and_cell->setPort(ID::A, and_sig.extract(0, 1));
and_cell->setPort(ID::B, and_sig.extract(1, 1));
and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire));
@ -141,7 +141,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
}
if (cases_vector.size() > 1) {
RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
RTLIL::Cell *or_cell = module->addCell(NEWER_ID, ID($reduce_or));
or_cell->setPort(ID::A, cases_vector);
or_cell->setPort(ID::Y, output);
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
@ -167,9 +167,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
// create state register
RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEWER_ID, fsm_data.state_bits);
RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
RTLIL::Cell *state_dff = module->addCell(NEWER_ID, "");
if (fsm_cell->getPort(ID::ARST).is_fully_const()) {
state_dff->type = ID($dff);
} else {
@ -191,7 +191,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
bool encoding_is_onehot = true;
RTLIL::Wire *state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
RTLIL::Wire *state_onehot = module->addWire(NEWER_ID, fsm_data.state_table.size());
for (size_t i = 0; i < fsm_data.state_table.size(); i++)
{
@ -212,7 +212,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
{
encoding_is_onehot = false;
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
RTLIL::Cell *eq_cell = module->addCell(NEWER_ID, ID($eq));
eq_cell->setPort(ID::A, sig_a);
eq_cell->setPort(ID::B, sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i));
@ -235,7 +235,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
}
else
{
RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
RTLIL::Wire *next_state_onehot = module->addWire(NEWER_ID, fsm_data.state_table.size());
for (size_t i = 0; i < fsm_data.state_table.size(); i++)
{
@ -285,7 +285,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
}
}
RTLIL::Cell *mux_cell = module->addCell(NEW_ID, ID($pmux));
RTLIL::Cell *mux_cell = module->addCell(NEWER_ID, ID($pmux));
mux_cell->setPort(ID::A, sig_a);
mux_cell->setPort(ID::B, sig_b);
mux_cell->setPort(ID::S, sig_s);

2
passes/hierarchy/flatten.cc
View file

@ -273,7 +273,7 @@ struct FlattenWorker
if (create_scopeinfo && cell_name.isPublic())
{
// The $scopeinfo's name will be changed below after removing the flattened cell
scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
scopeinfo = module->addCell(NEWER_ID, ID($scopeinfo));
scopeinfo->setParam(ID::TYPE, RTLIL::Const("module"));
for (auto const &attr : cell->attributes)

12
passes/hierarchy/hierarchy.cc
View file

@ -1370,7 +1370,7 @@ struct HierarchyPass : public Pass {
continue;
}
Wire *t = module->addWire(NEW_ID, GetSize(c));
Wire *t = module->addWire(NEWER_ID, GetSize(c));
new_sig.append(t);
update_port = true;
@ -1400,18 +1400,18 @@ struct HierarchyPass : public Pass {
if (GetSize(w) == 1) {
if (wand)
module->addReduceAnd(NEW_ID, sigs, w);
module->addReduceAnd(NEWER_ID, sigs, w);
else
module->addReduceOr(NEW_ID, sigs, w);
module->addReduceOr(NEWER_ID, sigs, w);
continue;
}
SigSpec s = sigs.extract(0, GetSize(w));
for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) {
if (wand)
s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w)));
s = module->And(NEWER_ID, s, sigs.extract(i, GetSize(w)));
else
s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w)));
s = module->Or(NEWER_ID, s, sigs.extract(i, GetSize(w)));
}
module->connect(w, s);
}
@ -1473,7 +1473,7 @@ struct HierarchyPass : public Pass {
if (w->port_input && !w->port_output)
sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed);
else
sig.append(module->addWire(NEW_ID, n));
sig.append(module->addWire(NEWER_ID, n));
}
if (!conn.second.is_fully_const() || !w->port_input || w->port_output)

4
passes/hierarchy/submod.cc
View file

@ -232,10 +232,10 @@ struct SubmodWorker
auto &b = old_sig[i];
// Prevents "ERROR: Mismatch in directionality ..." when flattening
if (!b.wire)
b = module->addWire(NEW_ID);
b = module->addWire(NEWER_ID);
// Prevents "Warning: multiple conflicting drivers ..."
else if (!it.second.is_int_driven[i])
b = module->addWire(NEW_ID);
b = module->addWire(NEWER_ID);
}
new_cell->setPort(new_wire->name, old_sig);
}

2
passes/memory/memory_bmux2rom.cc
View file

@ -60,7 +60,7 @@ struct MemoryBmux2RomPass : public Pass {
continue;
// Ok, let's do it.
Mem mem(module, NEW_ID, width, 0, 1 << abits);
Mem mem(module, NEWER_ID, width, 0, 1 << abits);
mem.attributes = cell->attributes;
MemInit init;

16
passes/memory/memory_bram.cc
View file

@ -841,7 +841,7 @@ grow_read_ports:;
// Swizzle read ports.
for (auto &port : mem.rd_ports) {
SigSpec new_data = module->addWire(NEW_ID, mem.width);
SigSpec new_data = module->addWire(NEWER_ID, mem.width);
Const new_init_value = Const(State::Sx, mem.width);
Const new_arst_value = Const(State::Sx, mem.width);
Const new_srst_value = Const(State::Sx, mem.width);
@ -920,7 +920,7 @@ grow_read_ports:;
if (GetSize(sig_addr) > bram.abits) {
SigSpec extra_addr = sig_addr.extract(bram.abits, GetSize(sig_addr) - bram.abits);
SigSpec extra_addr_sel = SigSpec(grid_a, GetSize(extra_addr));
addr_ok = module->Eq(NEW_ID, extra_addr, extra_addr_sel);
addr_ok = module->Eq(NEWER_ID, extra_addr, extra_addr_sel);
}
sig_addr.extend_u0(bram.abits);
@ -946,7 +946,7 @@ grow_read_ports:;
sig_en.append(port.en[stride * i + grid_d * bram.dbits]);
if (!addr_ok.empty())
sig_en = module->Mux(NEW_ID, SigSpec(0, GetSize(sig_en)), sig_en, addr_ok);
sig_en = module->Mux(NEWER_ID, SigSpec(0, GetSize(sig_en)), sig_en, addr_ok);
c->setPort(stringf("\\%sEN", pf), sig_en);
@ -961,13 +961,13 @@ grow_read_ports:;
auto &port = mem.rd_ports[pi.mapped_port];
SigSpec sig_data = port.data.extract(grid_d * bram.dbits, bram.dbits);
SigSpec bram_dout = module->addWire(NEW_ID, bram.dbits);
SigSpec bram_dout = module->addWire(NEWER_ID, bram.dbits);
c->setPort(stringf("\\%sDATA", pf), bram_dout);
SigSpec addr_ok_q = addr_ok;
if (port.clk_enable && !addr_ok.empty()) {
addr_ok_q = module->addWire(NEW_ID);
module->addDffe(NEW_ID, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity);
addr_ok_q = module->addWire(NEWER_ID);
module->addDffe(NEWER_ID, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity);
}
dout_cache[sig_data].first.append(addr_ok_q);
@ -976,7 +976,7 @@ grow_read_ports:;
if (pi.enable) {
SigSpec sig_en = port.en;
if (!addr_ok.empty())
sig_en = module->And(NEW_ID, sig_en, addr_ok);
sig_en = module->And(NEWER_ID, sig_en, addr_ok);
c->setPort(stringf("\\%sEN", pf), sig_en);
}
}
@ -994,7 +994,7 @@ grow_read_ports:;
else
{
log_assert(GetSize(it.first)*GetSize(it.second.first) == GetSize(it.second.second));
module->addPmux(NEW_ID, SigSpec(State::Sx, GetSize(it.first)), it.second.second, it.second.first, it.first);
module->addPmux(NEWER_ID, SigSpec(State::Sx, GetSize(it.first)), it.second.second, it.second.first, it.first);
}
}

6
passes/memory/memory_dff.cc
View file

@ -507,11 +507,11 @@ struct MemoryDffWorker
merger.remove_output_ff(bits);
if (ff.has_ce && !ff.pol_ce)
ff.sig_ce = module->LogicNot(NEW_ID, ff.sig_ce);
ff.sig_ce = module->LogicNot(NEWER_ID, ff.sig_ce);
if (ff.has_arst && !ff.pol_arst)
ff.sig_arst = module->LogicNot(NEW_ID, ff.sig_arst);
ff.sig_arst = module->LogicNot(NEWER_ID, ff.sig_arst);
if (ff.has_srst && !ff.pol_srst)
ff.sig_srst = module->LogicNot(NEW_ID, ff.sig_srst);
ff.sig_srst = module->LogicNot(NEWER_ID, ff.sig_srst);
port.clk = ff.sig_clk;
port.clk_enable = true;
port.clk_polarity = ff.pol_clk;

28
passes/memory/memory_libmap.cc
View file

@ -1625,8 +1625,8 @@ std::vector<SigSpec> generate_demux(Mem &mem, int wpidx, const Swizzle &swz) {
lo = new_lo;
hi = new_hi;
}
SigSpec in_range = mem.module->And(NEW_ID, mem.module->Ge(NEW_ID, addr, lo), mem.module->Lt(NEW_ID, addr, hi));
sig_a = mem.module->Mux(NEW_ID, Const(State::S0, GetSize(sig_a)), sig_a, in_range);
SigSpec in_range = mem.module->And(NEWER_ID, mem.module->Ge(NEWER_ID, addr, lo), mem.module->Lt(NEWER_ID, addr, hi));
sig_a = mem.module->Mux(NEWER_ID, Const(State::S0, GetSize(sig_a)), sig_a, in_range);
}
addr.extend_u0(swz.addr_shift + hi_bits, false);
SigSpec sig_s;
@ -1638,7 +1638,7 @@ std::vector<SigSpec> generate_demux(Mem &mem, int wpidx, const Swizzle &swz) {
if (GetSize(sig_s) == 0)
sig_y = sig_a;
else
sig_y = mem.module->Demux(NEW_ID, sig_a, sig_s);
sig_y = mem.module->Demux(NEWER_ID, sig_a, sig_s);
for (int i = 0; i < ((swz.addr_end - swz.addr_start) >> swz.addr_shift); i++) {
for (int j = 0; j < (1 << GetSize(swz.addr_mux_bits)); j++) {
int hi = ((swz.addr_start >> swz.addr_shift) + i) & ((1 << hi_bits) - 1);
@ -1664,14 +1664,14 @@ std::vector<SigSpec> generate_mux(Mem &mem, int rpidx, const Swizzle &swz) {
return {port.data};
}
if (port.clk_enable) {
SigSpec new_sig_s = mem.module->addWire(NEW_ID, GetSize(sig_s));
mem.module->addDffe(NEW_ID, port.clk, port.en, sig_s, new_sig_s, port.clk_polarity);
SigSpec new_sig_s = mem.module->addWire(NEWER_ID, GetSize(sig_s));
mem.module->addDffe(NEWER_ID, port.clk, port.en, sig_s, new_sig_s, port.clk_polarity);
sig_s = new_sig_s;
}
SigSpec sig_a = Const(State::Sx, GetSize(port.data) << hi_bits << GetSize(swz.addr_mux_bits));
for (int i = 0; i < ((swz.addr_end - swz.addr_start) >> swz.addr_shift); i++) {
for (int j = 0; j < (1 << GetSize(swz.addr_mux_bits)); j++) {
SigSpec sig = mem.module->addWire(NEW_ID, GetSize(port.data));
SigSpec sig = mem.module->addWire(NEWER_ID, GetSize(port.data));
int hi = ((swz.addr_start >> swz.addr_shift) + i) & ((1 << hi_bits) - 1);
int pos = (hi << GetSize(swz.addr_mux_bits) | j) * GetSize(port.data);
for (int k = 0; k < GetSize(port.data); k++)
@ -1679,7 +1679,7 @@ std::vector<SigSpec> generate_mux(Mem &mem, int rpidx, const Swizzle &swz) {
res.push_back(sig);
}
}
mem.module->addBmux(NEW_ID, sig_a, sig_s, port.data);
mem.module->addBmux(NEWER_ID, sig_a, sig_s, port.data);
return res;
}
@ -1709,7 +1709,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
if (pdef.clk_en) {
if (rpcfg.rd_en_to_clk_en) {
if (pdef.rdwr == RdWrKind::NoChange) {
clk_en = mem.module->Or(NEW_ID, rport.en, mem.module->ReduceOr(NEW_ID, wport.en));
clk_en = mem.module->Or(NEWER_ID, rport.en, mem.module->ReduceOr(NEWER_ID, wport.en));
} else {
clk_en = rport.en;
}
@ -1743,11 +1743,11 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
switch (pdef.clk_pol) {
case ClkPolKind::Posedge:
if (!clk_pol)
clk = mem.module->Not(NEW_ID, clk);
clk = mem.module->Not(NEWER_ID, clk);
break;
case ClkPolKind::Negedge:
if (clk_pol)
clk = mem.module->Not(NEW_ID, clk);
clk = mem.module->Not(NEWER_ID, clk);
break;
case ClkPolKind::Anyedge:
for (auto cell: cells)
@ -1852,7 +1852,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
cell->setPort(stringf("\\PORT_%s_WR_DATA", name), hw_wdata);
if (pdef.wrbe_separate) {
// TODO make some use of it
SigSpec en = mem.module->ReduceOr(NEW_ID, hw_wren);
SigSpec en = mem.module->ReduceOr(NEWER_ID, hw_wren);
cell->setPort(stringf("\\PORT_%s_WR_EN", name), en);
cell->setPort(stringf("\\PORT_%s_WR_BE", name), hw_wren);
if (cfg.def->width_mode != WidthMode::Single)
@ -1947,7 +1947,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), hw_val);
}
}
SigSpec hw_rdata = mem.module->addWire(NEW_ID, width);
SigSpec hw_rdata = mem.module->addWire(NEWER_ID, width);
cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata);
SigSpec lhs;
SigSpec rhs;
@ -1982,7 +1982,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
else if (pdef.rdsrstval == ResetValKind::NoUndef)
cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), Const(State::S0, width));
}
SigSpec hw_rdata = mem.module->addWire(NEW_ID, width);
SigSpec hw_rdata = mem.module->addWire(NEWER_ID, width);
cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata);
}
}
@ -2087,7 +2087,7 @@ void MemMapping::emit(const MemConfig &cfg) {
} else {
SigSpec sig = ccfg.used ? ccfg.clk : State::S0;
if (ccfg.used && ccfg.invert)
sig = mem.module->Not(NEW_ID, sig);
sig = mem.module->Not(NEWER_ID, sig);
cell->setPort(stringf("\\CLK_%s", cdef.name), sig);
}
}

4
passes/memory/memory_map.cc
View file

@ -89,12 +89,12 @@ struct MemoryMapWorker
if (decoder_cache.count(key) == 0) {
if (GetSize(addr_sig) < 2) {
decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val);
decoder_cache[key] = module->Eq(NEWER_ID, addr_sig, addr_val);
} else {
int split_at = GetSize(addr_sig) / 2;
RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at));
RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at));
decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq);
decoder_cache[key] = module->And(NEWER_ID, left_eq, right_eq);
}
}

12
passes/memory/memory_memx.cc
View file

@ -42,10 +42,10 @@ struct MemoryMemxPass : public Pass {
addr.extend_u0(32);
SigSpec res = mem.module->Nex(NEW_ID, mem.module->ReduceXor(NEW_ID, addr), mem.module->ReduceXor(NEW_ID, {addr, State::S1}));
SigSpec res = mem.module->Nex(NEWER_ID, mem.module->ReduceXor(NEWER_ID, addr), mem.module->ReduceXor(NEWER_ID, {addr, State::S1}));
if (start_addr != 0)
res = mem.module->LogicAnd(NEW_ID, res, mem.module->Ge(NEW_ID, addr, start_addr));
res = mem.module->LogicAnd(NEW_ID, res, mem.module->Lt(NEW_ID, addr, end_addr));
res = mem.module->LogicAnd(NEWER_ID, res, mem.module->Ge(NEWER_ID, addr, start_addr));
res = mem.module->LogicAnd(NEWER_ID, res, mem.module->Lt(NEWER_ID, addr, end_addr));
return res;
}
@ -63,14 +63,14 @@ struct MemoryMemxPass : public Pass {
log_id(module), log_id(mem.memid));
SigSpec addr_ok = make_addr_check(mem, port.addr);
Wire *raw_rdata = module->addWire(NEW_ID, GetSize(port.data));
module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data);
Wire *raw_rdata = module->addWire(NEWER_ID, GetSize(port.data));
module->addMux(NEWER_ID, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data);
port.data = raw_rdata;
}
for (auto &port : mem.wr_ports) {
SigSpec addr_ok = make_addr_check(mem, port.addr);
port.en = module->And(NEW_ID, port.en, addr_ok.repeat(GetSize(port.en)));
port.en = module->And(NEWER_ID, port.en, addr_ok.repeat(GetSize(port.en)));
}
mem.emit();

16
passes/memory/memory_share.cc
View file

@ -164,7 +164,7 @@ struct MemoryShareWorker
port2.addr = addr2;
mem.prepare_rd_merge(i, j, &initvals);
mem.widen_prep(wide_log2);
SigSpec new_data = module->addWire(NEW_ID, mem.width << wide_log2);
SigSpec new_data = module->addWire(NEWER_ID, mem.width << wide_log2);
module->connect(port1.data, new_data.extract(sub1 * mem.width, mem.width << port1.wide_log2));
module->connect(port2.data, new_data.extract(sub2 * mem.width, mem.width << port2.wide_log2));
for (int k = 0; k < wide_log2; k++)
@ -271,8 +271,8 @@ struct MemoryShareWorker
port1.data.replace(pos, port2.data.extract(pos, width));
new_en = port2.en[pos];
} else {
port1.data.replace(pos, module->Mux(NEW_ID, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos]));
new_en = module->Or(NEW_ID, port1.en[pos], port2.en[pos]);
port1.data.replace(pos, module->Mux(NEWER_ID, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos]));
new_en = module->Or(NEWER_ID, port1.en[pos], port2.en[pos]);
}
for (int k = pos; k < epos; k++)
port1.en[k] = new_en;
@ -424,21 +424,21 @@ struct MemoryShareWorker
RTLIL::SigSpec this_data = port2.data;
std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(port2.en);
RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
RTLIL::SigBit this_en_active = module->ReduceOr(NEWER_ID, this_en);
if (GetSize(last_addr) < GetSize(this_addr))
last_addr.extend_u0(GetSize(this_addr));
else
this_addr.extend_u0(GetSize(last_addr));
SigSpec new_addr = module->Mux(NEW_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active);
SigSpec new_addr = module->Mux(NEWER_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active);
port1.addr = SigSpec({new_addr, port1.addr.extract(0, port1.wide_log2)});
port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active);
port1.data = module->Mux(NEWER_ID, last_data, this_data, this_en_active);
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
RTLIL::Wire *grouped_en = module->addWire(NEWER_ID, 0);
for (int j = 0; j < int(this_en.size()); j++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
@ -451,7 +451,7 @@ struct MemoryShareWorker
en.append(RTLIL::SigSpec(grouped_en, groups_en[key]));
}
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
module->addMux(NEWER_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
port1.en = en;
port2.removed = true;

2
passes/opt/muxpack.cc
View file

@ -283,7 +283,7 @@ struct MuxpackWorker
else {
log_assert(cursor_cell->type == ID($mux));
b_sig.append(cursor_cell->getPort(ID::A));
s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
s_sig.append(module->LogicNot(NEWER_ID, cursor_cell->getPort(ID::S)));
}
remove_cells.insert(cursor_cell);
}

8
passes/opt/opt_demorgan.cc
View file

@ -99,8 +99,8 @@ void demorgan_worker(
//We are NOT inverted! Add an inverter
if(!srcinv)
{
auto inverted_b = m->addWire(NEW_ID);
m->addNot(NEW_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b));
auto inverted_b = m->addWire(NEWER_ID);
m->addNot(NEWER_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b));
insig[i] = inverted_b;
}
@ -166,8 +166,8 @@ void demorgan_worker(
//Add an inverter to the output
auto inverted_output = cell->getPort(ID::Y);
auto uninverted_output = m->addWire(NEW_ID);
m->addNot(NEW_ID, RTLIL::SigSpec(uninverted_output), inverted_output);
auto uninverted_output = m->addWire(NEWER_ID);
m->addNot(NEWER_ID, RTLIL::SigSpec(uninverted_output), inverted_output);
cell->setPort(ID::Y, uninverted_output);
}

60
passes/opt/opt_dff.cc
View file

@ -244,8 +244,8 @@ struct OptDffWorker
s2.append(it.second);
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y);
RTLIL::SigSpec y = module->addWire(NEWER_ID);
RTLIL::Cell *c = module->addNe(NEWER_ID, s1, s2, y);
if (make_gates) {
simplemap(module, c);
@ -258,9 +258,9 @@ struct OptDffWorker
if (item.second)
or_input.append(item.first);
else if (make_gates)
or_input.append(module->NotGate(NEW_ID, item.first));
or_input.append(module->NotGate(NEWER_ID, item.first));
else
or_input.append(module->Not(NEW_ID, item.first));
or_input.append(module->Not(NEWER_ID, item.first));
}
if (GetSize(or_input) == 0)
@ -269,8 +269,8 @@ struct OptDffWorker
if (GetSize(or_input) == 1)
return ctrl_t(or_input, true);
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y);
RTLIL::SigSpec y = module->addWire(NEWER_ID);
RTLIL::Cell *c = module->addReduceAnd(NEWER_ID, or_input, y);
if (make_gates) {
simplemap(module, c);
@ -298,13 +298,13 @@ struct OptDffWorker
if (item.second == final_pol)
or_input.append(item.first);
else if (make_gates)
or_input.append(module->NotGate(NEW_ID, item.first));
or_input.append(module->NotGate(NEWER_ID, item.first));
else
or_input.append(module->Not(NEW_ID, item.first));
or_input.append(module->Not(NEWER_ID, item.first));
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = final_pol ? module->addReduceOr(NEW_ID, or_input, y) : module->addReduceAnd(NEW_ID, or_input, y);
RTLIL::SigSpec y = module->addWire(NEWER_ID);
RTLIL::Cell *c = final_pol ? module->addReduceOr(NEWER_ID, or_input, y) : module->addReduceAnd(NEWER_ID, or_input, y);
if (make_gates) {
simplemap(module, c);
@ -348,9 +348,9 @@ struct OptDffWorker
if (!ff.pol_clr) {
module->connect(ff.sig_q[i], ff.sig_clr[i]);
} else if (ff.is_fine) {
module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNotGate(NEWER_ID, ff.sig_clr[i], ff.sig_q[i]);
} else {
module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNot(NEWER_ID, ff.sig_clr[i], ff.sig_q[i]);
}
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
i, log_id(cell), log_id(cell->type), log_id(module));
@ -451,34 +451,34 @@ struct OptDffWorker
SigSpec tmp;
if (ff.is_fine) {
if (ff.pol_set)
tmp = module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set);
tmp = module->MuxGate(NEWER_ID, ff.sig_ad, State::S1, ff.sig_set);
else
tmp = module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set);
tmp = module->MuxGate(NEWER_ID, State::S1, ff.sig_ad, ff.sig_set);
if (ff.pol_clr)
module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEWER_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);
else
module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEWER_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);
} else {
if (ff.pol_set)
tmp = module->Or(NEW_ID, ff.sig_ad, ff.sig_set);
tmp = module->Or(NEWER_ID, ff.sig_ad, ff.sig_set);
else
tmp = module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set));
tmp = module->Or(NEWER_ID, ff.sig_ad, module->Not(NEWER_ID, ff.sig_set));
if (ff.pol_clr)
module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q);
module->addAnd(NEWER_ID, tmp, module->Not(NEWER_ID, ff.sig_clr), ff.sig_q);
else
module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q);
module->addAnd(NEWER_ID, tmp, ff.sig_clr, ff.sig_q);
}
} else if (ff.has_arst) {
if (ff.is_fine) {
if (ff.pol_arst)
module->addMuxGate(NEW_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q);
module->addMuxGate(NEWER_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q);
else
module->addMuxGate(NEW_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q);
module->addMuxGate(NEWER_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q);
} else {
if (ff.pol_arst)
module->addMux(NEW_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q);
module->addMux(NEWER_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q);
else
module->addMux(NEW_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q);
module->addMux(NEWER_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q);
}
} else {
module->connect(ff.sig_q, ff.sig_ad);
@ -594,20 +594,20 @@ struct OptDffWorker
if (ff.has_ce && ff.ce_over_srst) {
if (!ff.pol_ce) {
if (ff.is_fine)
ff.sig_ce = module->NotGate(NEW_ID, ff.sig_ce);
ff.sig_ce = module->NotGate(NEWER_ID, ff.sig_ce);
else
ff.sig_ce = module->Not(NEW_ID, ff.sig_ce);
ff.sig_ce = module->Not(NEWER_ID, ff.sig_ce);
}
if (!ff.pol_srst) {
if (ff.is_fine)
ff.sig_srst = module->NotGate(NEW_ID, ff.sig_srst);
ff.sig_srst = module->NotGate(NEWER_ID, ff.sig_srst);
else
ff.sig_srst = module->Not(NEW_ID, ff.sig_srst);
ff.sig_srst = module->Not(NEWER_ID, ff.sig_srst);
}
if (ff.is_fine)
ff.sig_ce = module->AndGate(NEW_ID, ff.sig_ce, ff.sig_srst);
ff.sig_ce = module->AndGate(NEWER_ID, ff.sig_ce, ff.sig_srst);
else
ff.sig_ce = module->And(NEW_ID, ff.sig_ce, ff.sig_srst);
ff.sig_ce = module->And(NEWER_ID, ff.sig_ce, ff.sig_srst);
ff.pol_ce = true;
} else {
ff.pol_ce = ff.pol_srst;

68
passes/opt/opt_expr.cc
View file

@ -202,7 +202,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
if (grouped_bits[i].empty())
continue;
RTLIL::SigSpec new_y = module->addWire(NEW_ID, GetSize(grouped_bits[i]));
RTLIL::SigSpec new_y = module->addWire(NEWER_ID, GetSize(grouped_bits[i]));
RTLIL::SigSpec new_a, new_b;
RTLIL::SigSig new_conn;
@ -247,9 +247,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
else if (new_a[i] == State::S0 || new_a[i] == State::S1) {
undef_a.append(new_a[i]);
if (cell->type == ID($xor))
undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID, new_b[i]).as_bit() : new_b[i]);
undef_b.append(new_a[i] == State::S1 ? module->Not(NEWER_ID, new_b[i]).as_bit() : new_b[i]);
else if (cell->type == ID($xnor))
undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID, new_b[i]).as_bit());
undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEWER_ID, new_b[i]).as_bit());
else log_abort();
undef_y.append(new_y[i]);
}
@ -273,7 +273,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
}
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
RTLIL::Cell *c = module->addCell(NEWER_ID, cell->type);
c->setPort(ID::A, new_a);
c->parameters[ID::A_WIDTH] = new_a.size();
@ -612,9 +612,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.xor_buffer");
SigSpec sig_y;
if (cell->type == ID($xor))
sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a);
sig_y = (sig_b == State::S1 ? module->Not(NEWER_ID, sig_a).as_bit() : sig_a);
else if (cell->type == ID($_XOR_))
sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
sig_y = (sig_b == State::S1 ? module->NotGate(NEWER_ID, sig_a) : sig_a);
else log_abort();
replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y);
goto next_cell;
@ -623,12 +623,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.xnor_buffer");
SigSpec sig_y;
if (cell->type == ID($xnor)) {
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit());
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEWER_ID, sig_a).as_bit());
int width = cell->getParam(ID::Y_WIDTH).as_int();
sig_y.append(RTLIL::Const(State::S1, width-1));
}
else if (cell->type == ID($_XNOR_))
sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a));
sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEWER_ID, sig_a));
else log_abort();
replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y);
goto next_cell;
@ -698,7 +698,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!y_group_1.empty()) y_new_1 = b_group_1;
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->And(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->And(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
else
y_new_x = Const(State::S0, GetSize(y_group_x));
}
@ -707,16 +707,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!y_group_1.empty()) y_new_1 = Const(State::S1, GetSize(y_group_1));
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->Or(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->Or(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
else
y_new_x = Const(State::S1, GetSize(y_group_x));
}
} else if (cell->type.in(ID($xor), ID($xnor))) {
if (!y_group_0.empty()) y_new_0 = b_group_0;
if (!y_group_1.empty()) y_new_1 = module->Not(NEW_ID, b_group_1);
if (!y_group_1.empty()) y_new_1 = module->Not(NEWER_ID, b_group_1);
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->Xor(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->Xor(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor
y_new_x = Const(State::Sx, GetSize(y_group_x));
}
@ -779,11 +779,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec y_new_0, y_new_1;
if (flip) {
if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, module->Not(NEW_ID, s_group_0));
if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, s_group_1);
if (!y_group_0.empty()) y_new_0 = module->And(NEWER_ID, b_group_0, module->Not(NEWER_ID, s_group_0));
if (!y_group_1.empty()) y_new_1 = module->Or(NEWER_ID, b_group_1, s_group_1);
} else {
if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, s_group_0);
if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, module->Not(NEW_ID, s_group_1));
if (!y_group_0.empty()) y_new_0 = module->And(NEWER_ID, b_group_0, s_group_0);
if (!y_group_1.empty()) y_new_1 = module->Or(NEWER_ID, b_group_1, module->Not(NEWER_ID, s_group_1));
}
module->connect(y_group_0, y_new_0);
@ -996,12 +996,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigBit a = sig_a[i];
if (b == ((bi ^ ci) ? State::S1 : State::S0)) {
module->connect(sig_y[i], a);
module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a);
module->connect(sig_x[i], ci ? module->Not(NEWER_ID, a).as_bit() : a);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else if (a == (ci ? State::S1 : State::S0)) {
module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_y[i], bi ? module->Not(NEWER_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEWER_ID, b).as_bit() : b);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else
@ -1428,7 +1428,7 @@ skip_fine_alu:
/* sub, b is 0 */
RTLIL::SigSpec a = cell->getPort(ID::A);
a.extend_u0(y_width, is_signed);
module->connect(cell->getPort(ID::X), module->Not(NEW_ID, a));
module->connect(cell->getPort(ID::X), module->Not(NEWER_ID, a));
module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S1, y_width));
} else {
/* add */
@ -1733,10 +1733,10 @@ skip_identity:
cell->parameters[ID::A_SIGNED] = 0;
cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int()));
SigSpec y_wire = module->addWire(NEW_ID, y_size);
SigSpec y_wire = module->addWire(NEWER_ID, y_size);
cell->setPort(ID::Y, y_wire);
module->addShl(NEW_ID, Const(State::S1, 1), y_wire, sig_y);
module->addShl(NEWER_ID, Const(State::S1, 1), y_wire, sig_y);
}
did_something = true;
goto next_cell;
@ -1889,13 +1889,13 @@ skip_identity:
// Truncating division is the same as flooring division, except when
// the result is negative and there is a remainder - then trunc = floor + 1
if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) {
Wire *flooring = module->addWire(NEW_ID, sig_y.size());
Wire *flooring = module->addWire(NEWER_ID, sig_y.size());
cell->setPort(ID::Y, flooring);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero);
module->addAdd(NEW_ID, flooring, should_add, sig_y);
SigSpec rem_nonzero = module->ReduceOr(NEWER_ID, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEWER_ID, a_sign, rem_nonzero);
module->addAdd(NEWER_ID, flooring, should_add, sig_y);
}
cell->check();
@ -1917,11 +1917,11 @@ skip_identity:
SigSpec truncating = sig_a.extract(0, exp);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec extend_bit = module->And(NEW_ID, a_sign, rem_nonzero);
SigSpec rem_nonzero = module->ReduceOr(NEWER_ID, sig_a.extract(0, exp));
SigSpec extend_bit = module->And(NEWER_ID, a_sign, rem_nonzero);
truncating.append(extend_bit);
module->addPos(NEW_ID, truncating, sig_y, true);
module->addPos(NEWER_ID, truncating, sig_y, true);
}
else
{
@ -2004,7 +2004,7 @@ skip_identity:
int sz = cur - prev;
bool last = cur == GetSize(sig_y);
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
RTLIL::Cell *c = module->addCell(NEWER_ID, cell->type);
c->setPort(ID::A, sig_a.extract(prev, sz));
c->setPort(ID::B, sig_b.extract(prev, sz));
c->setPort(ID::BI, sig_bi);
@ -2014,7 +2014,7 @@ skip_identity:
RTLIL::SigSpec new_co = sig_co.extract(prev, sz);
if (p.second != State::Sx) {
module->connect(new_co[sz-1], p.second);
RTLIL::Wire *dummy = module->addWire(NEW_ID);
RTLIL::Wire *dummy = module->addWire(NEWER_ID);
new_co[sz-1] = dummy;
}
c->setPort(ID::CO, new_co);
@ -2181,14 +2181,14 @@ skip_alu_split:
{
condition = stringf("unsigned X<%s", log_signal(const_sig));
replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
module->addLogicNot(NEW_ID, var_high_sig, cell->getPort(ID::Y));
module->addLogicNot(NEWER_ID, var_high_sig, cell->getPort(ID::Y));
remove = true;
}
if (cmp_type == ID($ge))
{
condition = stringf("unsigned X>=%s", log_signal(const_sig));
replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
module->addReduceOr(NEW_ID, var_high_sig, cell->getPort(ID::Y));
module->addReduceOr(NEWER_ID, var_high_sig, cell->getPort(ID::Y));
remove = true;
}
}
@ -2230,7 +2230,7 @@ skip_alu_split:
{
condition = "signed X>=0";
replacement = stringf("X[%d]", var_width - 1);
module->addLogicNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID::Y));
module->addLogicNot(NEWER_ID, var_sig[var_width - 1], cell->getPort(ID::Y));
remove = true;
}
}

4
passes/opt/opt_hier.cc
View file

@ -137,7 +137,7 @@ struct ModuleIndex {
rhs.replace(constant_outputs);
log_assert(rhs.is_fully_const());
parent.module->connect(value.extract(chunk.offset, chunk.width), rhs);
SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("const_output"), chunk.width);
SigSpec dummy = parent.module->addWire(NEWER_ID_SUFFIX("const_output"), chunk.width);
for (int i = 0; i < chunk.width; i++)
value[chunk.offset + i] = dummy[i];
}
@ -182,7 +182,7 @@ struct ModuleIndex {
severed_port_bits.sort_and_unify();
for (auto chunk : severed_port_bits.chunks()) {
SigSpec &value = instantiation->connections_.at(chunk.wire->name);
SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("tie_together"), chunk.width);
SigSpec dummy = parent.module->addWire(NEWER_ID_SUFFIX("tie_together"), chunk.width);
for (int i = 0; i < chunk.width; i++)
value[chunk.offset + i] = dummy[i];
}

2
passes/opt/opt_mem.cc
View file

@ -125,7 +125,7 @@ struct OptMemPass : public Pass {
module->connect(port.data[bidx], bit);
} else {
// The FF will most likely be redundant, but it's up to opt_dff to deal with this.
FfData ff(module, &initvals, NEW_ID);
FfData ff(module, &initvals, NEWER_ID);
ff.width = 1;
ff.has_clk = true;
ff.sig_clk = port.clk;

4
passes/opt/opt_mem_feedback.cc
View file

@ -120,7 +120,7 @@ struct OptMemFeedbackWorker
sig1.append(it.first);
sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0);
}
terms.append(module->Ne(NEW_ID, sig1, sig2));
terms.append(module->Ne(NEWER_ID, sig1, sig2));
}
if (olden != State::S1)
@ -130,7 +130,7 @@ struct OptMemFeedbackWorker
terms = State::S1;
if (GetSize(terms) > 1)
terms = module->ReduceAnd(NEW_ID, terms);
terms = module->ReduceAnd(NEWER_ID, terms);
return conditions_logic_cache[key] = terms;
}

4
passes/opt/opt_reduce.cc
View file

@ -128,13 +128,13 @@ struct OptReduceWorker
if (this_s.size() > 1)
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
RTLIL::Cell *reduce_or_cell = module->addCell(NEWER_ID, ID($reduce_or));
reduce_or_cell->setPort(ID::A, this_s);
reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
RTLIL::Wire *reduce_or_wire = module->addWire(NEWER_ID);
this_s = RTLIL::SigSpec(reduce_or_wire);
reduce_or_cell->setPort(ID::Y, this_s);
}

12
passes/opt/opt_share.cc
View file

@ -196,7 +196,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
for (auto &operand : muxed_operands) {
operand.sig.extend_u0(max_width, operand.is_signed);
if (operand.sign != muxed_operands[0].sign)
operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
operand = ExtSigSpec(module->Neg(NEWER_ID, operand.sig, operand.is_signed));
}
for (const auto& p : ports) {
@ -219,7 +219,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
RTLIL::SigSpec shared_pmux_s;
// Make a new wire to avoid false equivalence with whatever the former shared output was connected to.
Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width);
Wire *new_out = module->addWire(NEWER_ID, conn_op_offset + conn_width);
SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width);
for (int i = 0; i < GetSize(ports); i++) {
@ -241,14 +241,14 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
SigSpec mux_to_oper;
if (GetSize(shared_pmux_s) == 1) {
mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
mux_to_oper = module->Mux(NEWER_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
} else {
mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
mux_to_oper = module->Pmux(NEWER_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
}
if (shared_op->type.in(ID($alu))) {
shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(ID::X, module->addWire(NEWER_ID, GetSize(new_out)));
shared_op->setPort(ID::CO, module->addWire(NEWER_ID, GetSize(new_out)));
}
bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);

4
passes/opt/peepopt_formal_clockgateff.pmg
View file

@ -50,8 +50,8 @@ code
// instead of the latch. We don't delete the latch in case its output is
// used to drive other nodes. If it isn't, it will be trivially removed by
// clean
SigSpec flopped_en = module->addWire(NEW_ID);
module->addDff(NEW_ID, clk, en, flopped_en, true, latch->get_src_attribute());
SigSpec flopped_en = module->addWire(NEWER_ID);
module->addDff(NEWER_ID, clk, en, flopped_en, true, latch->get_src_attribute());
and_gate->setPort(latched_en_port_name, flopped_en);
did_something = true;

6
passes/opt/peepopt_shiftmul_left.pmg
View file

@ -129,7 +129,7 @@ code
if (bit == SigBit(State::Sm))
padbits++;
SigSpec padwire = module->addWire(NEW_ID, padbits);
SigSpec padwire = module->addWire(NEWER_ID, padbits);
for (int i = new_y.size() - 1; i >= 0; i--)
if (new_y[i] == SigBit(State::Sm)) {
@ -148,8 +148,8 @@ code
shift->setPort(\B, new_b);
shift->setParam(\B_WIDTH, GetSize(new_b));
} else {
SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1);
module->addNeg(NEW_ID, new_b, b_neg);
SigSpec b_neg = module->addWire(NEWER_ID, GetSize(new_b) + 1);
module->addNeg(NEWER_ID, new_b, b_neg);
shift->setPort(\B, b_neg);
shift->setParam(\B_WIDTH, GetSize(b_neg));
}

12
passes/opt/pmux2shiftx.cc
View file

@ -680,9 +680,9 @@ struct Pmux2ShiftxPass : public Pass {
// creat cmp signal
SigSpec cmp = perm_sig;
if (perm_xormask.as_bool())
cmp = module->Xor(NEW_ID, cmp, perm_xormask, false, src);
cmp = module->Xor(NEWER_ID, cmp, perm_xormask, false, src);
if (offset.as_bool())
cmp = module->Sub(NEW_ID, cmp, offset, false, src);
cmp = module->Sub(NEWER_ID, cmp, offset, false, src);
// create enable signal
SigBit en = State::S1;
@ -690,8 +690,8 @@ struct Pmux2ShiftxPass : public Pass {
Const enable_mask(State::S0, max_choice+1);
for (auto &it : perm_choices)
enable_mask.set(it.first.as_int(), State::S1);
en = module->addWire(NEW_ID);
module->addShift(NEW_ID, enable_mask, cmp, en, false, src);
en = module->addWire(NEWER_ID);
module->addShift(NEWER_ID, enable_mask, cmp, en, false, src);
}
// create data signal
@ -710,8 +710,8 @@ struct Pmux2ShiftxPass : public Pass {
// create shiftx cell
SigSpec shifted_cmp = {cmp, SigSpec(State::S0, width_bits)};
SigSpec outsig = module->addWire(NEW_ID, width);
Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src);
SigSpec outsig = module->addWire(NEWER_ID, width);
Cell *c = module->addShiftx(NEWER_ID, data, shifted_cmp, outsig, false, src);
updated_S.append(en);
updated_B.append(outsig);
log(" created $shiftx cell %s.\n", log_id(c));

92
passes/opt/share.cc
View file

@ -207,13 +207,13 @@ struct ShareWorker
sig_b2.extend_u0(GetSize(sig_b), p2.is_signed);
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, sig_a2, sig_a1, act, sig_a));
sig_a = module->addWire(NEWER_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEWER_ID, sig_a2, sig_a1, act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b));
sig_b = module->addWire(NEWER_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEWER_ID, sig_b2, sig_b1, act, sig_b));
}
Macc::term_t p;
@ -284,13 +284,13 @@ struct ShareWorker
RTLIL::SigSpec sig_b = m1.terms[i].in_b;
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a));
sig_a = module->addWire(NEWER_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEWER_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b));
sig_b = module->addWire(NEWER_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEWER_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b));
}
Macc::term_t p;
@ -307,13 +307,13 @@ struct ShareWorker
RTLIL::SigSpec sig_b = m2.terms[i].in_b;
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a));
sig_a = module->addWire(NEWER_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEWER_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b));
sig_b = module->addWire(NEWER_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEWER_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b));
}
Macc::term_t p;
@ -326,10 +326,10 @@ struct ShareWorker
if (supercell)
{
RTLIL::SigSpec sig_y = module->addWire(NEW_ID, width);
RTLIL::SigSpec sig_y = module->addWire(NEWER_ID, width);
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEWER_ID, sig_y, c1->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEWER_ID, sig_y, c2->getPort(ID::Y)));
supercell->setParam(ID::Y_WIDTH, width);
supercell->setPort(ID::Y, sig_y);
@ -541,20 +541,20 @@ struct ShareWorker
a1.extend_u0(a_width, a_signed);
a2.extend_u0(a_width, a_signed);
RTLIL::SigSpec a = module->addWire(NEW_ID, a_width);
supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a));
RTLIL::SigSpec a = module->addWire(NEWER_ID, a_width);
supercell_aux.insert(module->addMux(NEWER_ID, a2, a1, act, a));
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Wire *y = module->addWire(NEWER_ID, y_width);
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1->type);
supercell->parameters[ID::A_SIGNED] = a_signed;
supercell->parameters[ID::A_WIDTH] = a_width;
supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a);
supercell->setPort(ID::Y, y);
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
supercell_aux.insert(module->addPos(NEWER_ID, y, y1));
supercell_aux.insert(module->addPos(NEWER_ID, y, y2));
supercell_aux.insert(supercell);
return supercell;
@ -656,17 +656,17 @@ struct ShareWorker
b1.extend_u0(b_width, b_signed);
b2.extend_u0(b_width, b_signed);
RTLIL::SigSpec a = module->addWire(NEW_ID, a_width);
RTLIL::SigSpec b = module->addWire(NEW_ID, b_width);
RTLIL::SigSpec a = module->addWire(NEWER_ID, a_width);
RTLIL::SigSpec b = module->addWire(NEWER_ID, b_width);
supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a));
supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b));
supercell_aux.insert(module->addMux(NEWER_ID, a2, a1, act, a));
supercell_aux.insert(module->addMux(NEWER_ID, b2, b1, act, b));
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Wire *y = module->addWire(NEWER_ID, y_width);
RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEWER_ID, y_width) : nullptr;
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEWER_ID, y_width) : nullptr;
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1->type);
supercell->parameters[ID::A_SIGNED] = a_signed;
supercell->parameters[ID::B_SIGNED] = b_signed;
supercell->parameters[ID::A_WIDTH] = a_width;
@ -676,9 +676,9 @@ struct ShareWorker
supercell->setPort(ID::B, b);
supercell->setPort(ID::Y, y);
if (c1->type == ID($alu)) {
RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID);
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci));
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi));
RTLIL::Wire *ci = module->addWire(NEWER_ID), *bi = module->addWire(NEWER_ID);
supercell_aux.insert(module->addMux(NEWER_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci));
supercell_aux.insert(module->addMux(NEWER_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi));
supercell->setPort(ID::CI, ci);
supercell->setPort(ID::BI, bi);
supercell->setPort(ID::CO, co);
@ -686,13 +686,13 @@ struct ShareWorker
}
supercell->check();
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
supercell_aux.insert(module->addPos(NEWER_ID, y, y1));
supercell_aux.insert(module->addPos(NEWER_ID, y, y2));
if (c1->type == ID($alu)) {
supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEWER_ID, co, c1->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEWER_ID, co, c2->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEWER_ID, x, c1->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEWER_ID, x, c2->getPort(ID::X)));
}
supercell_aux.insert(supercell);
@ -701,7 +701,7 @@ struct ShareWorker
if (c1->type == ID($macc))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1->type);
supercell_aux.insert(supercell);
share_macc(c1, c2, act, supercell, &supercell_aux);
supercell->check();
@ -710,16 +710,16 @@ struct ShareWorker
if (c1->type.in(ID($memrd), ID($memrd_v2)))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1);
RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR);
RTLIL::SigSpec addr2 = c2->getPort(ID::ADDR);
if (GetSize(addr1) < GetSize(addr2))
addr1.extend_u0(GetSize(addr2));
else
addr2.extend_u0(GetSize(addr1));
supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEWER_ID, addr2, addr1, act) : addr1);
supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1));
supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA)));
supercell_aux.insert(module->addPos(NEWER_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA)));
supercell_aux.insert(supercell);
return supercell;
}
@ -1065,18 +1065,18 @@ struct ShareWorker
RTLIL::SigSpec make_cell_activation_logic(const pool<ssc_pair_t> &activation_patterns, pool<RTLIL::Cell*> &supercell_aux)
{
RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
RTLIL::Wire *all_cases_wire = module->addWire(NEWER_ID, 0);
for (auto &p : activation_patterns) {
all_cases_wire->width++;
supercell_aux.insert(module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1)));
supercell_aux.insert(module->addEq(NEWER_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1)));
}
if (all_cases_wire->width == 1)
return all_cases_wire;
RTLIL::Wire *result_wire = module->addWire(NEW_ID);
supercell_aux.insert(module->addReduceOr(NEW_ID, all_cases_wire, result_wire));
RTLIL::Wire *result_wire = module->addWire(NEWER_ID);
supercell_aux.insert(module->addReduceOr(NEWER_ID, all_cases_wire, result_wire));
return result_wire;
}

2
passes/opt/wreduce.cc
View file

@ -511,7 +511,7 @@ struct WreduceWorker
continue;
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
Wire *nw = module->addWire(NEWER_ID, GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
}

6
passes/pmgen/README.md
View file

@ -367,9 +367,9 @@ test-case generation. For example:
...
generate 10 0
SigSpec Y = port(ff, \D);
SigSpec A = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
SigSpec B = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
module->addMul(NEW_ID, A, B, Y, rng(2));
SigSpec A = module->addWire(NEWER_ID, GetSize(Y) - rng(GetSize(Y)/2));
SigSpec B = module->addWire(NEWER_ID, GetSize(Y) - rng(GetSize(Y)/2));
module->addMul(NEWER_ID, A, B, Y, rng(2));
endmatch
The expression `rng(n)` returns a non-negative integer less than `n`.

4
passes/pmgen/generate.h
View file

@ -78,7 +78,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
while (modcnt < maxmodcnt)
{
int submodcnt = 0, itercnt = 0, cellcnt = 0;
Module *mod = design->addModule(NEW_ID);
Module *mod = design->addModule(NEWER_ID);
while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000)
{
@ -130,7 +130,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
for (auto mod : mods) {
Cell *c = m->addCell(mod->name, mod->name);
for (auto port : mod->ports) {
Wire *w = m->addWire(NEW_ID, GetSize(mod->wire(port)));
Wire *w = m->addWire(NEWER_ID, GetSize(mod->wire(port)));
c->setPort(port, w);
}
}

14
passes/pmgen/test_pmgen.cc
View file

@ -58,11 +58,11 @@ void reduce_chain(test_pmgen_pm &pm)
Cell *c;
if (last_cell->type == ID($_AND_))
c = pm.module->addReduceAnd(NEW_ID, A, Y);
c = pm.module->addReduceAnd(NEWER_ID, A, Y);
else if (last_cell->type == ID($_OR_))
c = pm.module->addReduceOr(NEW_ID, A, Y);
c = pm.module->addReduceOr(NEWER_ID, A, Y);
else if (last_cell->type == ID($_XOR_))
c = pm.module->addReduceXor(NEW_ID, A, Y);
c = pm.module->addReduceXor(NEWER_ID, A, Y);
else
log_abort();
@ -87,11 +87,11 @@ void reduce_tree(test_pmgen_pm &pm)
Cell *c;
if (st.first->type == ID($_AND_))
c = pm.module->addReduceAnd(NEW_ID, A, Y);
c = pm.module->addReduceAnd(NEWER_ID, A, Y);
else if (st.first->type == ID($_OR_))
c = pm.module->addReduceOr(NEW_ID, A, Y);
c = pm.module->addReduceOr(NEWER_ID, A, Y);
else if (st.first->type == ID($_XOR_))
c = pm.module->addReduceXor(NEW_ID, A, Y);
c = pm.module->addReduceXor(NEWER_ID, A, Y);
else
log_abort();
@ -112,7 +112,7 @@ void opt_eqpmux(test_pmgen_pm &pm)
log_signal(Y), log_id(st.eq), log_id(st.ne), log_id(st.pmux));
pm.autoremove(st.pmux);
Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(ID::Y), Y);
Cell *c = pm.module->addMux(NEWER_ID, NE, EQ, st.eq->getPort(ID::Y), Y);
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
}

42
passes/pmgen/test_pmgen.pmg
View file

@ -14,19 +14,19 @@ match first
select first->type.in($_AND_, $_OR_, $_XOR_)
filter !non_first_cells.count(first)
generate
SigSpec A = module->addWire(NEW_ID);
SigSpec B = module->addWire(NEW_ID);
SigSpec Y = module->addWire(NEW_ID);
SigSpec A = module->addWire(NEWER_ID);
SigSpec B = module->addWire(NEWER_ID);
SigSpec Y = module->addWire(NEWER_ID);
switch (rng(3))
{
case 0:
module->addAndGate(NEW_ID, A, B, Y);
module->addAndGate(NEWER_ID, A, B, Y);
break;
case 1:
module->addOrGate(NEW_ID, A, B, Y);
module->addOrGate(NEWER_ID, A, B, Y);
break;
case 2:
module->addXorGate(NEW_ID, A, B, Y);
module->addXorGate(NEWER_ID, A, B, Y);
break;
}
endmatch
@ -82,10 +82,10 @@ match next
index <IdString> next->type === chain.back().first->type
index <SigSpec> port(next, \Y) === port(chain.back().first, chain.back().second)
generate 10
SigSpec A = module->addWire(NEW_ID);
SigSpec B = module->addWire(NEW_ID);
SigSpec A = module->addWire(NEWER_ID);
SigSpec B = module->addWire(NEWER_ID);
SigSpec Y = port(chain.back().first, chain.back().second);
Cell *c = module->addAndGate(NEW_ID, A, B, Y);
Cell *c = module->addAndGate(NEWER_ID, A, B, Y);
c->type = chain.back().first->type;
endmatch
@ -121,10 +121,10 @@ match eq
set eq_inB port(eq, \B)
set eq_ne_signed param(eq, \A_SIGNED).as_bool()
generate 100 10
SigSpec A = module->addWire(NEW_ID, rng(7)+1);
SigSpec B = module->addWire(NEW_ID, rng(7)+1);
SigSpec Y = module->addWire(NEW_ID);
module->addEq(NEW_ID, A, B, Y, rng(2));
SigSpec A = module->addWire(NEWER_ID, rng(7)+1);
SigSpec B = module->addWire(NEWER_ID, rng(7)+1);
SigSpec Y = module->addWire(NEWER_ID);
module->addEq(NEWER_ID, A, B, Y, rng(2));
endmatch
match pmux
@ -137,16 +137,16 @@ generate 100 10
int numsel = rng(4) + 1;
int idx = rng(numsel);
SigSpec A = module->addWire(NEW_ID, width);
SigSpec Y = module->addWire(NEW_ID, width);
SigSpec A = module->addWire(NEWER_ID, width);
SigSpec Y = module->addWire(NEWER_ID, width);
SigSpec B, S;
for (int i = 0; i < numsel; i++) {
B.append(module->addWire(NEW_ID, width));
S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_ID));
B.append(module->addWire(NEWER_ID, width));
S.append(i == idx ? port(eq, \Y) : module->addWire(NEWER_ID));
}
module->addPmux(NEW_ID, A, B, S, Y);
module->addPmux(NEWER_ID, A, B, S, Y);
endmatch
match ne
@ -169,11 +169,11 @@ generate 100 10
if (GetSize(Y))
Y = Y[rng(GetSize(Y))];
else
Y = module->addWire(NEW_ID);
Y = module->addWire(NEWER_ID);
} else {
Y = module->addWire(NEW_ID);
Y = module->addWire(NEWER_ID);
}
module->addNe(NEW_ID, A, B, Y, rng(2));
module->addNe(NEWER_ID, A, B, Y, rng(2));
endmatch
match pmux2

16
passes/proc/proc_dff.cc
View file

@ -66,16 +66,16 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++)
{
const auto& [sync_value, rule] = *it;
const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEW_ID, rule->signal);
const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEWER_ID, rule->signal);
// If pos_trig is true, we have priority at this point in the tree so
// set a bit if sync_value has a set bit. Otherwise, defer to the rest
// of the priority tree
sig_sr_set = mod->Mux(NEW_ID, sig_sr_set, sync_value, pos_trig);
sig_sr_set = mod->Mux(NEWER_ID, sig_sr_set, sync_value, pos_trig);
// Same deal with clear bit
const auto sync_value_inv = mod->Not(NEW_ID, sync_value);
sig_sr_clr = mod->Mux(NEW_ID, sig_sr_clr, sync_value_inv, pos_trig);
const auto sync_value_inv = mod->Not(NEWER_ID, sync_value);
sig_sr_clr = mod->Mux(NEWER_ID, sig_sr_clr, sync_value_inv, pos_trig);
}
std::stringstream sstr;
@ -217,12 +217,12 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
// (with appropriate negation)
RTLIL::SigSpec triggers;
for (const auto &[_, it] : async_rules)
triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEW_ID, it->signal));
triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEWER_ID, it->signal));
// Put this into the dummy sync rule so it can be treated the same
// as ones coming from the module
single_async_rule.type = RTLIL::SyncType::ST1;
single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers);
single_async_rule.signal = mod->ReduceOr(NEWER_ID, triggers);
single_async_rule.actions.push_back(RTLIL::SigSig(sig, rstval));
// Replace existing rules with this new rule
@ -239,9 +239,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
if (async_rules.size() == 1 && async_rules.front().first == sig) {
const auto& [_, rule] = async_rules.front();
if (rule->type == RTLIL::SyncType::ST1)
insig = mod->Mux(NEW_ID, insig, sig, rule->signal);
insig = mod->Mux(NEWER_ID, insig, sig, rule->signal);
else
insig = mod->Mux(NEW_ID, sig, insig, rule->signal);
insig = mod->Mux(NEWER_ID, sig, insig, rule->signal);
async_rules.clear();
}

10
passes/proc/proc_dlatch.cc
View file

@ -246,20 +246,20 @@ struct proc_dlatch_db_t
if (rule.match == State::S1)
and_bits.append(rule.signal);
else if (rule.match == State::S0)
and_bits.append(module->Not(NEW_ID, rule.signal, false, src));
and_bits.append(module->Not(NEWER_ID, rule.signal, false, src));
else
and_bits.append(module->Eq(NEW_ID, rule.signal, rule.match, false, src));
and_bits.append(module->Eq(NEWER_ID, rule.signal, rule.match, false, src));
}
if (!rule.children.empty()) {
SigSpec or_bits;
for (int k : rule.children)
or_bits.append(make_hold(k, src));
and_bits.append(module->ReduceOr(NEW_ID, or_bits, false, src));
and_bits.append(module->ReduceOr(NEWER_ID, or_bits, false, src));
}
if (GetSize(and_bits) == 2)
and_bits = module->And(NEW_ID, and_bits[0], and_bits[1], false, src);
and_bits = module->And(NEWER_ID, and_bits[0], and_bits[1], false, src);
log_assert(GetSize(and_bits) == 1);
rules_sig[n] = and_bits[0];
@ -429,7 +429,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
SigSpec lhs = latches_bits.first.extract(offset, width);
SigSpec rhs = latches_bits.second.extract(offset, width);
Cell *cell = db.module->addDlatch(NEW_ID, db.module->Not(NEW_ID, db.make_hold(n, src)), rhs, lhs);
Cell *cell = db.module->addDlatch(NEWER_ID, db.module->Not(NEWER_ID, db.make_hold(n, src)), rhs, lhs);
cell->set_src_attribute(src);
db.generated_dlatches.insert(cell);

6
passes/proc/proc_memwr.cc
View file

@ -42,7 +42,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
priority_mask.set(prev_port_ids[i], State::S1);
prev_port_ids.push_back(port_id);
RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2));
RTLIL::Cell *cell = mod->addCell(NEWER_ID, ID($memwr_v2));
cell->attributes = memwr.attributes;
cell->setParam(ID::MEMID, Const(memwr.memid.str()));
cell->setParam(ID::ABITS, GetSize(memwr.address));
@ -55,10 +55,10 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
for (auto sr2 : proc->syncs) {
if (sr2->type == RTLIL::SyncType::ST0) {
log_assert(sr2->mem_write_actions.empty());
enable = mod->Mux(NEW_ID, Const(State::S0, GetSize(enable)), enable, sr2->signal);
enable = mod->Mux(NEWER_ID, Const(State::S0, GetSize(enable)), enable, sr2->signal);
} else if (sr2->type == RTLIL::SyncType::ST1) {
log_assert(sr2->mem_write_actions.empty());
enable = mod->Mux(NEW_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal);
enable = mod->Mux(NEWER_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal);
}
}
cell->setPort(ID::EN, enable);

4
passes/proc/proc_rom.cc
View file

@ -151,8 +151,8 @@ struct RomWorker
}
// Ok, let's do it.
SigSpec rdata = module->addWire(NEW_ID, GetSize(lhs));
Mem mem(module, NEW_ID, GetSize(lhs), 0, 1 << abits);
SigSpec rdata = module->addWire(NEWER_ID, GetSize(lhs));
Mem mem(module, NEWER_ID, GetSize(lhs), 0, 1 << abits);
mem.attributes = sw->attributes;
Const::Builder builder(mem.size * GetSize(lhs));

18
passes/sat/assertpmux.cc
View file

@ -100,12 +100,12 @@ struct AssertpmuxWorker
if (muxport_actsignal.count(muxport) == 0) {
if (portidx == 0)
muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(ID::S));
muxport_actsignal[muxport] = module->LogicNot(NEWER_ID, cell->getPort(ID::S));
else
muxport_actsignal[muxport] = cell->getPort(ID::S)[portidx-1];
}
output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx])));
output.append(module->LogicAnd(NEWER_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx])));
}
output.sort_and_unify();
@ -113,7 +113,7 @@ struct AssertpmuxWorker
if (GetSize(output) == 0)
output = State::S0;
else if (GetSize(output) > 1)
output = module->ReduceOr(NEW_ID, output);
output = module->ReduceOr(NEWER_ID, output);
sigbit_actsignals[bit] = output.as_bit();
}
@ -138,7 +138,7 @@ struct AssertpmuxWorker
if (GetSize(output) == 0)
output = State::S0;
else if (GetSize(output) > 1)
output = module->ReduceOr(NEW_ID, output);
output = module->ReduceOr(NEWER_ID, output);
sigspec_actsignals[sig] = output.as_bit();
}
@ -157,13 +157,13 @@ struct AssertpmuxWorker
SigSpec cnt(State::S0, cntbits);
for (int i = 0; i < swidth; i++)
cnt = module->Add(NEW_ID, cnt, sel[i]);
cnt = module->Add(NEWER_ID, cnt, sel[i]);
SigSpec assert_a = module->Le(NEW_ID, cnt, SigSpec(1, cntbits));
SigSpec assert_a = module->Le(NEWER_ID, cnt, SigSpec(1, cntbits));
SigSpec assert_en;
if (flag_noinit)
assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID)));
assert_en.append(module->LogicNot(NEWER_ID, module->Initstate(NEWER_ID)));
if (!flag_always)
assert_en.append(get_activation(pmux->getPort(ID::Y)));
@ -172,9 +172,9 @@ struct AssertpmuxWorker
assert_en = State::S1;
if (GetSize(assert_en) == 2)
assert_en = module->LogicAnd(NEW_ID, assert_en[0], assert_en[1]);
assert_en = module->LogicAnd(NEWER_ID, assert_en[0], assert_en[1]);
Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en);
Cell *assert_cell = module->addAssert(NEWER_ID, assert_a, assert_en);
if (pmux->attributes.count(ID::src) != 0)
assert_cell->attributes[ID::src] = pmux->attributes.at(ID::src);

110
passes/sat/async2sync.cc
View file

@ -95,27 +95,27 @@ struct Async2syncPass : public Pass {
if (trg_width == 0) {
if (initstate == State::S0)
initstate = module->Initstate(NEW_ID);
initstate = module->Initstate(NEWER_ID);
SigBit sig_en = cell->getPort(ID::EN);
cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate));
cell->setPort(ID::EN, module->And(NEWER_ID, sig_en, initstate));
} else {
SigBit sig_en = cell->getPort(ID::EN);
SigSpec sig_args = cell->getPort(ID::ARGS);
bool trg_polarity = cell->getParam(ID(TRG_POLARITY)).as_bool();
SigBit sig_trg = cell->getPort(ID::TRG);
Wire *sig_en_q = module->addWire(NEW_ID);
Wire *sig_args_q = module->addWire(NEW_ID, GetSize(sig_args));
Wire *sig_en_q = module->addWire(NEWER_ID);
Wire *sig_args_q = module->addWire(NEWER_ID, GetSize(sig_args));
sig_en_q->attributes.emplace(ID::init, State::S0);
module->addDff(NEW_ID, sig_trg, sig_en, sig_en_q, trg_polarity, cell->get_src_attribute());
module->addDff(NEW_ID, sig_trg, sig_args, sig_args_q, trg_polarity, cell->get_src_attribute());
module->addDff(NEWER_ID, sig_trg, sig_en, sig_en_q, trg_polarity, cell->get_src_attribute());
module->addDff(NEWER_ID, sig_trg, sig_args, sig_args_q, trg_polarity, cell->get_src_attribute());
cell->setPort(ID::EN, sig_en_q);
cell->setPort(ID::ARGS, sig_args_q);
if (cell->type == ID($check)) {
SigBit sig_a = cell->getPort(ID::A);
Wire *sig_a_q = module->addWire(NEW_ID);
Wire *sig_a_q = module->addWire(NEWER_ID);
sig_a_q->attributes.emplace(ID::init, State::S1);
module->addDff(NEW_ID, sig_trg, sig_a, sig_a_q, trg_polarity, cell->get_src_attribute());
module->addDff(NEWER_ID, sig_trg, sig_a, sig_a_q, trg_polarity, cell->get_src_attribute());
cell->setPort(ID::A, sig_a_q);
}
}
@ -152,38 +152,38 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q);
Wire *new_d = module->addWire(NEW_ID, ff.width);
Wire *new_q = module->addWire(NEW_ID, ff.width);
Wire *new_d = module->addWire(NEWER_ID, ff.width);
Wire *new_q = module->addWire(NEWER_ID, ff.width);
SigSpec sig_set = ff.sig_set;
SigSpec sig_clr = ff.sig_clr;
if (!ff.pol_set) {
if (!ff.is_fine)
sig_set = module->Not(NEW_ID, sig_set);
sig_set = module->Not(NEWER_ID, sig_set);
else
sig_set = module->NotGate(NEW_ID, sig_set);
sig_set = module->NotGate(NEWER_ID, sig_set);
}
if (ff.pol_clr) {
if (!ff.is_fine)
sig_clr = module->Not(NEW_ID, sig_clr);
sig_clr = module->Not(NEWER_ID, sig_clr);
else
sig_clr = module->NotGate(NEW_ID, sig_clr);
sig_clr = module->NotGate(NEWER_ID, sig_clr);
}
if (!ff.is_fine) {
SigSpec tmp = module->Or(NEW_ID, ff.sig_d, sig_set);
module->addAnd(NEW_ID, tmp, sig_clr, new_d);
SigSpec tmp = module->Or(NEWER_ID, ff.sig_d, sig_set);
module->addAnd(NEWER_ID, tmp, sig_clr, new_d);
tmp = module->Or(NEW_ID, new_q, sig_set);
module->addAnd(NEW_ID, tmp, sig_clr, ff.sig_q);
tmp = module->Or(NEWER_ID, new_q, sig_set);
module->addAnd(NEWER_ID, tmp, sig_clr, ff.sig_q);
} else {
SigSpec tmp = module->OrGate(NEW_ID, ff.sig_d, sig_set);
module->addAndGate(NEW_ID, tmp, sig_clr, new_d);
SigSpec tmp = module->OrGate(NEWER_ID, ff.sig_d, sig_set);
module->addAndGate(NEWER_ID, tmp, sig_clr, new_d);
tmp = module->OrGate(NEW_ID, new_q, sig_set);
module->addAndGate(NEW_ID, tmp, sig_clr, ff.sig_q);
tmp = module->OrGate(NEWER_ID, new_q, sig_set);
module->addAndGate(NEWER_ID, tmp, sig_clr, ff.sig_q);
}
ff.sig_d = new_d;
@ -198,24 +198,24 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q);
Wire *new_d = module->addWire(NEW_ID, ff.width);
Wire *new_q = module->addWire(NEW_ID, ff.width);
Wire *new_d = module->addWire(NEWER_ID, ff.width);
Wire *new_q = module->addWire(NEWER_ID, ff.width);
if (ff.pol_aload) {
if (!ff.is_fine) {
module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q);
module->addMux(NEW_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d);
module->addMux(NEWER_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q);
module->addMux(NEWER_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d);
} else {
module->addMuxGate(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q);
module->addMuxGate(NEW_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d);
module->addMuxGate(NEWER_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q);
module->addMuxGate(NEWER_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d);
}
} else {
if (!ff.is_fine) {
module->addMux(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q);
module->addMux(NEW_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d);
module->addMux(NEWER_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q);
module->addMux(NEWER_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d);
} else {
module->addMuxGate(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q);
module->addMuxGate(NEW_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d);
module->addMuxGate(NEWER_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q);
module->addMuxGate(NEWER_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d);
}
}
@ -231,18 +231,18 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q);
Wire *new_q = module->addWire(NEW_ID, ff.width);
Wire *new_q = module->addWire(NEWER_ID, ff.width);
if (ff.pol_arst) {
if (!ff.is_fine)
module->addMux(NEW_ID, new_q, ff.val_arst, ff.sig_arst, ff.sig_q);
module->addMux(NEWER_ID, new_q, ff.val_arst, ff.sig_arst, ff.sig_q);
else
module->addMuxGate(NEW_ID, new_q, ff.val_arst[0], ff.sig_arst, ff.sig_q);
module->addMuxGate(NEWER_ID, new_q, ff.val_arst[0], ff.sig_arst, ff.sig_q);
} else {
if (!ff.is_fine)
module->addMux(NEW_ID, ff.val_arst, new_q, ff.sig_arst, ff.sig_q);
module->addMux(NEWER_ID, ff.val_arst, new_q, ff.sig_arst, ff.sig_q);
else
module->addMuxGate(NEW_ID, ff.val_arst[0], new_q, ff.sig_arst, ff.sig_q);
module->addMuxGate(NEWER_ID, ff.val_arst[0], new_q, ff.sig_arst, ff.sig_q);
}
ff.sig_q = new_q;
@ -265,21 +265,21 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q);
Wire *new_q = module->addWire(NEW_ID, ff.width);
Wire *new_q = module->addWire(NEWER_ID, ff.width);
Wire *new_d;
if (ff.has_aload) {
new_d = module->addWire(NEW_ID, ff.width);
new_d = module->addWire(NEWER_ID, ff.width);
if (ff.pol_aload) {
if (!ff.is_fine)
module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d);
module->addMux(NEWER_ID, new_q, ff.sig_ad, ff.sig_aload, new_d);
else
module->addMuxGate(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d);
module->addMuxGate(NEWER_ID, new_q, ff.sig_ad, ff.sig_aload, new_d);
} else {
if (!ff.is_fine)
module->addMux(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, new_d);
module->addMux(NEWER_ID, ff.sig_ad, new_q, ff.sig_aload, new_d);
else
module->addMuxGate(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, new_d);
module->addMuxGate(NEWER_ID, ff.sig_ad, new_q, ff.sig_aload, new_d);
}
} else {
new_d = new_q;
@ -291,36 +291,36 @@ struct Async2syncPass : public Pass {
if (!ff.pol_set) {
if (!ff.is_fine)
sig_set = module->Not(NEW_ID, sig_set);
sig_set = module->Not(NEWER_ID, sig_set);
else
sig_set = module->NotGate(NEW_ID, sig_set);
sig_set = module->NotGate(NEWER_ID, sig_set);
}
if (ff.pol_clr) {
if (!ff.is_fine)
sig_clr = module->Not(NEW_ID, sig_clr);
sig_clr = module->Not(NEWER_ID, sig_clr);
else
sig_clr = module->NotGate(NEW_ID, sig_clr);
sig_clr = module->NotGate(NEWER_ID, sig_clr);
}
if (!ff.is_fine) {
SigSpec tmp = module->Or(NEW_ID, new_d, sig_set);
module->addAnd(NEW_ID, tmp, sig_clr, ff.sig_q);
SigSpec tmp = module->Or(NEWER_ID, new_d, sig_set);
module->addAnd(NEWER_ID, tmp, sig_clr, ff.sig_q);
} else {
SigSpec tmp = module->OrGate(NEW_ID, new_d, sig_set);
module->addAndGate(NEW_ID, tmp, sig_clr, ff.sig_q);
SigSpec tmp = module->OrGate(NEWER_ID, new_d, sig_set);
module->addAndGate(NEWER_ID, tmp, sig_clr, ff.sig_q);
}
} else if (ff.has_arst) {
if (ff.pol_arst) {
if (!ff.is_fine)
module->addMux(NEW_ID, new_d, ff.val_arst, ff.sig_arst, ff.sig_q);
module->addMux(NEWER_ID, new_d, ff.val_arst, ff.sig_arst, ff.sig_q);
else
module->addMuxGate(NEW_ID, new_d, ff.val_arst[0], ff.sig_arst, ff.sig_q);
module->addMuxGate(NEWER_ID, new_d, ff.val_arst[0], ff.sig_arst, ff.sig_q);
} else {
if (!ff.is_fine)
module->addMux(NEW_ID, ff.val_arst, new_d, ff.sig_arst, ff.sig_q);
module->addMux(NEWER_ID, ff.val_arst, new_d, ff.sig_arst, ff.sig_q);
else
module->addMuxGate(NEW_ID, ff.val_arst[0], new_d, ff.sig_arst, ff.sig_q);
module->addMuxGate(NEWER_ID, ff.val_arst[0], new_d, ff.sig_arst, ff.sig_q);
}
} else {
module->connect(ff.sig_q, new_d);

60
passes/sat/clk2fflogic.cc
View file

@ -66,31 +66,31 @@ struct Clk2fflogicPass : public Pass {
SampledSig sample_control(Module *module, SigSpec sig, bool polarity, bool is_fine) {
if (!polarity) {
if (is_fine)
sig = module->NotGate(NEW_ID, sig);
sig = module->NotGate(NEWER_ID, sig);
else
sig = module->Not(NEW_ID, sig);
sig = module->Not(NEWER_ID, sig);
}
std::string sig_str = log_signal(sig);
sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
Wire *sampled_sig = module->addWire(NEWER_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
sampled_sig->attributes[ID::init] = RTLIL::Const(State::S0, GetSize(sig));
if (is_fine)
module->addFfGate(NEW_ID, sig, sampled_sig);
module->addFfGate(NEWER_ID, sig, sampled_sig);
else
module->addFf(NEW_ID, sig, sampled_sig);
module->addFf(NEWER_ID, sig, sampled_sig);
return {sampled_sig, sig};
}
// Active-high trigger signal for an edge-triggered control signal. Initial values is low/non-edge.
SigSpec sample_control_edge(Module *module, SigSpec sig, bool polarity, bool is_fine) {
std::string sig_str = log_signal(sig);
sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
Wire *sampled_sig = module->addWire(NEWER_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
sampled_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S1 : State::S0, GetSize(sig));
if (is_fine)
module->addFfGate(NEW_ID, sig, sampled_sig);
module->addFfGate(NEWER_ID, sig, sampled_sig);
else
module->addFf(NEW_ID, sig, sampled_sig);
return module->Eqx(NEW_ID, {sampled_sig, sig}, polarity ? SigSpec {State::S0, State::S1} : SigSpec {State::S1, State::S0});
module->addFf(NEWER_ID, sig, sampled_sig);
return module->Eqx(NEWER_ID, {sampled_sig, sig}, polarity ? SigSpec {State::S0, State::S1} : SigSpec {State::S1, State::S0});
}
// Sampled and current value of a data signal.
SampledSig sample_data(Module *module, SigSpec sig, RTLIL::Const init, bool is_fine, bool set_attribute = false) {
@ -98,14 +98,14 @@ struct Clk2fflogicPass : public Pass {
sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
Wire *sampled_sig = module->addWire(NEWER_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
sampled_sig->attributes[ID::init] = init;
Cell *cell;
if (is_fine)
cell = module->addFfGate(NEW_ID, sig, sampled_sig);
cell = module->addFfGate(NEWER_ID, sig, sampled_sig);
else
cell = module->addFf(NEW_ID, sig, sampled_sig);
cell = module->addFf(NEWER_ID, sig, sampled_sig);
if (set_attribute) {
for (auto &chunk : sig.chunks())
@ -118,15 +118,15 @@ struct Clk2fflogicPass : public Pass {
}
SigSpec mux(Module *module, SigSpec a, SigSpec b, SigSpec s, bool is_fine) {
if (is_fine)
return module->MuxGate(NEW_ID, a, b, s);
return module->MuxGate(NEWER_ID, a, b, s);
else
return module->Mux(NEW_ID, a, b, s);
return module->Mux(NEWER_ID, a, b, s);
}
SigSpec bitwise_sr(Module *module, SigSpec a, SigSpec s, SigSpec r, bool is_fine) {
if (is_fine)
return module->AndGate(NEW_ID, module->OrGate(NEW_ID, a, s), module->NotGate(NEW_ID, r));
return module->AndGate(NEWER_ID, module->OrGate(NEWER_ID, a, s), module->NotGate(NEWER_ID, r));
else
return module->And(NEW_ID, module->Or(NEW_ID, a, s), module->Not(NEW_ID, r));
return module->And(NEWER_ID, module->Or(NEWER_ID, a, s), module->Not(NEWER_ID, r));
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
@ -183,9 +183,9 @@ struct Clk2fflogicPass : public Pass {
i, log_id(module), log_id(mem.memid), log_signal(port.clk),
log_signal(port.addr), log_signal(port.data));
Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", log_id(mem.memid), i, log_signal(port.clk))));
Wire *past_clk = module->addWire(NEWER_ID_SUFFIX(stringf("%s#%d#past_clk#%s", log_id(mem.memid), i, log_signal(port.clk))));
past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
module->addFf(NEW_ID, port.clk, past_clk);
module->addFf(NEWER_ID, port.clk, past_clk);
SigSpec clock_edge_pattern;
@ -197,19 +197,19 @@ struct Clk2fflogicPass : public Pass {
clock_edge_pattern.append(State::S0);
}
SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
SigSpec clock_edge = module->Eqx(NEWER_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", log_id(mem.memid), i)), GetSize(port.en));
module->addFf(NEW_ID, port.en, en_q);
SigSpec en_q = module->addWire(NEWER_ID_SUFFIX(stringf("%s#%d#en_q", log_id(mem.memid), i)), GetSize(port.en));
module->addFf(NEWER_ID, port.en, en_q);
SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", log_id(mem.memid), i)), GetSize(port.addr));
module->addFf(NEW_ID, port.addr, addr_q);
SigSpec addr_q = module->addWire(NEWER_ID_SUFFIX(stringf("%s#%d#addr_q", log_id(mem.memid), i)), GetSize(port.addr));
module->addFf(NEWER_ID, port.addr, addr_q);
SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", log_id(mem.memid), i)), GetSize(port.data));
module->addFf(NEW_ID, port.data, data_q);
SigSpec data_q = module->addWire(NEWER_ID_SUFFIX(stringf("%s#%d#data_q", log_id(mem.memid), i)), GetSize(port.data));
module->addFf(NEWER_ID, port.data, data_q);
port.clk = State::S0;
port.en = module->Mux(NEW_ID, Const(0, GetSize(en_q)), en_q, clock_edge);
port.en = module->Mux(NEWER_ID, Const(0, GetSize(en_q)), en_q, clock_edge);
port.addr = addr_q;
port.data = data_q;
@ -237,10 +237,10 @@ struct Clk2fflogicPass : public Pass {
if (trg_width == 0) {
if (initstate == State::S0)
initstate = module->Initstate(NEW_ID);
initstate = module->Initstate(NEWER_ID);
SigBit sig_en = cell->getPort(ID::EN);
cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate));
cell->setPort(ID::EN, module->And(NEWER_ID, sig_en, initstate));
} else {
SigBit sig_en = cell->getPort(ID::EN);
SigSpec sig_args = cell->getPort(ID::ARGS);
@ -254,9 +254,9 @@ struct Clk2fflogicPass : public Pass {
SigSpec sig_args_sampled = sample_data(module, sig_args, Const(State::S0, GetSize(sig_args)), false, false).sampled;
SigBit sig_en_sampled = sample_data(module, sig_en, State::S0, false, false).sampled;
SigBit sig_trg_combined = module->ReduceOr(NEW_ID, sig_trg_sampled);
SigBit sig_trg_combined = module->ReduceOr(NEWER_ID, sig_trg_sampled);
cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined));
cell->setPort(ID::EN, module->And(NEWER_ID, sig_en_sampled, sig_trg_combined));
cell->setPort(ID::ARGS, sig_args_sampled);
if (cell->type == ID($check)) {
SigBit sig_a = cell->getPort(ID::A);

16
passes/sat/cutpoint.cc
View file

@ -102,7 +102,7 @@ struct CutpointPass : public Pass {
if (wire->port_output)
output_wires.push_back(wire);
for (auto wire : output_wires)
module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_ID, GetSize(wire)));
module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEWER_ID, GetSize(wire)));
continue;
}
@ -115,13 +115,13 @@ struct CutpointPass : public Pass {
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
for (auto &conn : cell->connections()) {
if (cell->output(conn.first))
module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second)));
module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEWER_ID, GetSize(conn.second)));
}
RTLIL::Cell *scopeinfo = nullptr;
auto cell_name = cell->name;
if (flag_scopeinfo && cell_name.isPublic()) {
auto scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
auto scopeinfo = module->addCell(NEWER_ID, ID($scopeinfo));
scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox"));
for (auto const &attr : cell->attributes)
@ -142,9 +142,9 @@ struct CutpointPass : public Pass {
for (auto wire : module->selected_wires()) {
if (wire->port_output) {
log("Making output wire %s.%s a cutpoint.\n", log_id(module), log_id(wire));
Wire *new_wire = module->addWire(NEW_ID, wire);
Wire *new_wire = module->addWire(NEWER_ID, wire);
module->swap_names(wire, new_wire);
module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEW_ID, GetSize(new_wire)));
module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEWER_ID, GetSize(new_wire)));
wire->port_id = 0;
wire->port_input = false;
wire->port_output = false;
@ -169,7 +169,7 @@ struct CutpointPass : public Pass {
}
if (bit_count == 0)
continue;
SigSpec dummy = module->addWire(NEW_ID, bit_count);
SigSpec dummy = module->addWire(NEWER_ID, bit_count);
bit_count = 0;
for (auto &bit : sig) {
if (cutpoint_bits.count(bit))
@ -193,7 +193,7 @@ struct CutpointPass : public Pass {
}
for (auto wire : rewrite_wires) {
Wire *new_wire = module->addWire(NEW_ID, wire);
Wire *new_wire = module->addWire(NEWER_ID, wire);
SigSpec lhs, rhs, sig = sigmap(wire);
for (int i = 0; i < GetSize(sig); i++)
if (!cutpoint_bits.count(sig[i])) {
@ -213,7 +213,7 @@ struct CutpointPass : public Pass {
for (auto chunk : sig.chunks()) {
SigSpec s(chunk);
module->connect(s, flag_undef ? Const(State::Sx, GetSize(s)) : module->Anyseq(NEW_ID, GetSize(s)));
module->connect(s, flag_undef ? Const(State::Sx, GetSize(s)) : module->Anyseq(NEWER_ID, GetSize(s)));
}
}
}

8
passes/sat/expose.cc
View file

@ -472,7 +472,7 @@ struct ExposePass : public Pass {
if (!w->port_input) {
w->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
wire_map[w] = NEW_ID;
wire_map[w] = NEWER_ID;
}
}
else
@ -542,7 +542,7 @@ struct ExposePass : public Pass {
dff_map_info_t &info = dq.second;
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEWER_ID, 0);
for (auto &cell_name : info.cells) {
RTLIL::Cell *cell = module->cell(cell_name);
@ -578,7 +578,7 @@ struct ExposePass : public Pass {
if (info.clk_polarity) {
module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
} else {
RTLIL::Cell *c = module->addCell(NEW_ID, ID($not));
RTLIL::Cell *c = module->addCell(NEWER_ID, ID($not));
c->parameters[ID::A_SIGNED] = 0;
c->parameters[ID::A_WIDTH] = 1;
c->parameters[ID::Y_WIDTH] = 1;
@ -594,7 +594,7 @@ struct ExposePass : public Pass {
if (info.arst_polarity) {
module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
} else {
RTLIL::Cell *c = module->addCell(NEW_ID, ID($not));
RTLIL::Cell *c = module->addCell(NEWER_ID, ID($not));
c->parameters[ID::A_SIGNED] = 0;
c->parameters[ID::A_WIDTH] = 1;
c->parameters[ID::Y_WIDTH] = 1;

20
passes/sat/fmcombine.cc
View file

@ -121,9 +121,9 @@ struct FmcombineWorker
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
SigSpec gold_q = gold->getPort(ID::Q);
SigSpec gate_q = gate->getPort(ID::Q);
SigSpec en = module->Initstate(NEW_ID);
SigSpec eq = module->Eq(NEW_ID, gold_q, gate_q);
module->addAssume(NEW_ID, eq, en);
SigSpec en = module->Initstate(NEWER_ID);
SigSpec eq = module->Eq(NEWER_ID, gold_q, gate_q);
module->addAssume(NEWER_ID, eq, en);
}
}
}
@ -163,7 +163,7 @@ struct FmcombineWorker
SigSpec A = import_sig(conn.second, "_gold");
SigSpec B = import_sig(conn.second, "_gate");
SigBit EQ = module->Eq(NEW_ID, A, B);
SigBit EQ = module->Eq(NEWER_ID, A, B);
for (auto bit : sigmap({A, B}))
data_bit_to_eq_net[bit] = EQ;
@ -205,7 +205,7 @@ struct FmcombineWorker
if (GetSize(antecedent) > 1) {
if (reduce_db.count(antecedent) == 0)
reduce_db[antecedent] = module->ReduceAnd(NEW_ID, antecedent);
reduce_db[antecedent] = module->ReduceAnd(NEWER_ID, antecedent);
antecedent = reduce_db.at(antecedent);
}
@ -214,22 +214,22 @@ struct FmcombineWorker
if (GetSize(consequent) > 1) {
if (reduce_db.count(consequent) == 0)
reduce_db[consequent] = module->ReduceAnd(NEW_ID, consequent);
reduce_db[consequent] = module->ReduceAnd(NEWER_ID, consequent);
consequent = reduce_db.at(consequent);
}
if (opts.fwd)
module->addAssume(NEW_ID, consequent, antecedent);
module->addAssume(NEWER_ID, consequent, antecedent);
if (opts.bwd)
{
if (invert_db.count(antecedent) == 0)
invert_db[antecedent] = module->Not(NEW_ID, antecedent);
invert_db[antecedent] = module->Not(NEWER_ID, antecedent);
if (invert_db.count(consequent) == 0)
invert_db[consequent] = module->Not(NEW_ID, consequent);
invert_db[consequent] = module->Not(NEWER_ID, consequent);
module->addAssume(NEW_ID, invert_db.at(antecedent), invert_db.at(consequent));
module->addAssume(NEWER_ID, invert_db.at(antecedent), invert_db.at(consequent));
}
}
}

22
passes/sat/fminit.cc
View file

@ -131,8 +131,8 @@ struct FminitPass : public Pass {
}
if (!final_lhs.empty()) {
SigSpec eq = module->Eq(NEW_ID, final_lhs, final_rhs);
module->addAssume(NEW_ID, eq, State::S1);
SigSpec eq = module->Eq(NEWER_ID, final_lhs, final_rhs);
module->addAssume(NEWER_ID, eq, State::S1);
}
}
@ -152,13 +152,13 @@ struct FminitPass : public Pass {
{
SigSpec insig = i > 0 ? ctrlsig.at(i-1) : State::S0;
Wire *outwire = module->addWire(NEW_ID);
Wire *outwire = module->addWire(NEWER_ID);
outwire->attributes[ID::init] = i > 0 ? State::S0 : State::S1;
if (clksig.empty())
module->addFf(NEW_ID, insig, outwire);
module->addFf(NEWER_ID, insig, outwire);
else
module->addDff(NEW_ID, clksig, insig, outwire, clockedge);
module->addDff(NEWER_ID, clksig, insig, outwire, clockedge);
ctrlsig.push_back(outwire);
ctrlsig_latched.push_back(SigSpec());
@ -166,14 +166,14 @@ struct FminitPass : public Pass {
if (i+1 == GetSize(it.second) && ctrlsig_latched[i].empty())
{
Wire *ffwire = module->addWire(NEW_ID);
Wire *ffwire = module->addWire(NEWER_ID);
ffwire->attributes[ID::init] = State::S0;
SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]);
SigSpec outsig = module->Or(NEWER_ID, ffwire, ctrlsig[i]);
if (clksig.empty())
module->addFf(NEW_ID, outsig, ffwire);
module->addFf(NEWER_ID, outsig, ffwire);
else
module->addDff(NEW_ID, clksig, outsig, ffwire, clockedge);
module->addDff(NEWER_ID, clksig, outsig, ffwire, clockedge);
ctrlsig_latched[i] = outsig;
}
@ -192,8 +192,8 @@ struct FminitPass : public Pass {
}
if (!final_lhs.empty()) {
SigSpec eq = module->Eq(NEW_ID, final_lhs, final_rhs);
module->addAssume(NEW_ID, eq, ctrl);
SigSpec eq = module->Eq(NEWER_ID, final_lhs, final_rhs);
module->addAssume(NEWER_ID, eq, ctrl);
}
}
}

18
passes/sat/formalff.cc
View file

@ -420,7 +420,7 @@ struct PropagateWorker
replaced_clk_inputs.emplace_back(ReplacedPort {port, i, it->second});
if (it->second) {
bit = module->Not(NEW_ID, bit);
bit = module->Not(NEWER_ID, bit);
}
}
}
@ -445,7 +445,7 @@ struct PropagateWorker
if (add_attribute) {
Wire *clk_wire = bit.wire;
if (bit.offset != 0 || GetSize(bit.wire) != 1) {
clk_wire = module->addWire(NEW_ID);
clk_wire = module->addWire(NEWER_ID);
module->connect(RTLIL::SigBit(clk_wire), bit);
}
clk_wire->attributes[ID::replaced_by_gclk] = polarity ? State::S1 : State::S0;
@ -802,9 +802,9 @@ struct FormalFfPass : public Pass {
log_debug("patching rd port\n");
changed = true;
rd_port.clk = gate_clock;
SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEW_ID, sig_gate));
SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEWER_ID, sig_gate));
SigSpec en_mask = SigSpec(en_bit, GetSize(rd_port.en));
rd_port.en = module->And(NEW_ID, rd_port.en, en_mask);
rd_port.en = module->And(NEWER_ID, rd_port.en, en_mask);
}
}
for (auto &wr_port : mem.wr_ports) {
@ -812,9 +812,9 @@ struct FormalFfPass : public Pass {
log_debug("patching wr port\n");
changed = true;
wr_port.clk = gate_clock;
SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEW_ID, sig_gate));
SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEWER_ID, sig_gate));
SigSpec en_mask = SigSpec(en_bit, GetSize(wr_port.en));
wr_port.en = module->And(NEW_ID, wr_port.en, en_mask);
wr_port.en = module->And(NEWER_ID, wr_port.en, en_mask);
}
}
if (changed)
@ -900,7 +900,7 @@ struct FormalFfPass : public Pass {
auto clk_wire = ff.sig_clk.is_wire() ? ff.sig_clk.as_wire() : nullptr;
if (clk_wire == nullptr) {
clk_wire = module->addWire(NEW_ID);
clk_wire = module->addWire(NEWER_ID);
module->connect(RTLIL::SigBit(clk_wire), ff.sig_clk);
}
@ -982,9 +982,9 @@ struct FormalFfPass : public Pass {
SigBit clk = pair.first;
if (pair.second)
clk = module->Not(NEW_ID, clk);
clk = module->Not(NEWER_ID, clk);
module->addAssume(NEW_ID, clk, State::S1);
module->addAssume(NEWER_ID, clk, State::S1);
}
}

6
passes/sat/freduce.cc
View file

@ -716,7 +716,7 @@ struct FreduceWorker
log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
RTLIL::Wire *dummy_wire = module->addWire(NEWER_ID);
for (auto &port : drv->connections_)
if (ct.cell_output(drv->type, port.first))
sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
@ -725,9 +725,9 @@ struct FreduceWorker
{
if (inv_sig.size() == 0)
{
inv_sig = module->addWire(NEW_ID);
inv_sig = module->addWire(NEWER_ID);
RTLIL::Cell *inv_cell = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *inv_cell = module->addCell(NEWER_ID, ID($_NOT_));
inv_cell->setPort(ID::A, grp[0].bit);
inv_cell->setPort(ID::Y, inv_sig);
}

62
passes/sat/miter.cc
View file

@ -146,12 +146,12 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
SigSpec w = miter_module->addWire("\\cross_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
gold_cell->setPort(gold_wire->name, w);
if (flag_ignore_gold_x) {
RTLIL::SigSpec w_x = miter_module->addWire(NEW_ID, GetSize(w));
RTLIL::SigSpec w_x = miter_module->addWire(NEWER_ID, GetSize(w));
for (int i = 0; i < GetSize(w); i++)
miter_module->addEqx(NEW_ID, w[i], State::Sx, w_x[i]);
RTLIL::SigSpec w_any = miter_module->And(NEW_ID, miter_module->Anyseq(NEW_ID, GetSize(w)), w_x);
RTLIL::SigSpec w_masked = miter_module->And(NEW_ID, w, miter_module->Not(NEW_ID, w_x));
w = miter_module->And(NEW_ID, w_any, w_masked);
miter_module->addEqx(NEWER_ID, w[i], State::Sx, w_x[i]);
RTLIL::SigSpec w_any = miter_module->And(NEWER_ID, miter_module->Anyseq(NEWER_ID, GetSize(w)), w_x);
RTLIL::SigSpec w_masked = miter_module->And(NEWER_ID, w, miter_module->Not(NEWER_ID, w_x));
w = miter_module->And(NEWER_ID, w_any, w_masked);
}
gate_cell->setPort(gold_wire->name, w);
continue;
@ -181,9 +181,9 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (flag_ignore_gold_x)
{
RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width);
RTLIL::SigSpec gold_x = miter_module->addWire(NEWER_ID, w_gold->width);
for (int i = 0; i < w_gold->width; i++) {
RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, ID($eqx));
RTLIL::Cell *eqx_cell = miter_module->addCell(NEWER_ID, ID($eqx));
eqx_cell->parameters[ID::A_WIDTH] = 1;
eqx_cell->parameters[ID::B_WIDTH] = 1;
eqx_cell->parameters[ID::Y_WIDTH] = 1;
@ -194,10 +194,10 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
eqx_cell->setPort(ID::Y, gold_x.extract(i, 1));
}
RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width);
RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width);
RTLIL::SigSpec gold_masked = miter_module->addWire(NEWER_ID, w_gold->width);
RTLIL::SigSpec gate_masked = miter_module->addWire(NEWER_ID, w_gate->width);
RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, ID($or));
RTLIL::Cell *or_gold_cell = miter_module->addCell(NEWER_ID, ID($or));
or_gold_cell->parameters[ID::A_WIDTH] = w_gold->width;
or_gold_cell->parameters[ID::B_WIDTH] = w_gold->width;
or_gold_cell->parameters[ID::Y_WIDTH] = w_gold->width;
@ -207,7 +207,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
or_gold_cell->setPort(ID::B, gold_x);
or_gold_cell->setPort(ID::Y, gold_masked);
RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, ID($or));
RTLIL::Cell *or_gate_cell = miter_module->addCell(NEWER_ID, ID($or));
or_gate_cell->parameters[ID::A_WIDTH] = w_gate->width;
or_gate_cell->parameters[ID::B_WIDTH] = w_gate->width;
or_gate_cell->parameters[ID::Y_WIDTH] = w_gate->width;
@ -217,7 +217,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
or_gate_cell->setPort(ID::B, gold_x);
or_gate_cell->setPort(ID::Y, gate_masked);
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx));
RTLIL::Cell *eq_cell = miter_module->addCell(NEWER_ID, ID($eqx));
eq_cell->parameters[ID::A_WIDTH] = w_gold->width;
eq_cell->parameters[ID::B_WIDTH] = w_gate->width;
eq_cell->parameters[ID::Y_WIDTH] = 1;
@ -225,12 +225,12 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
eq_cell->parameters[ID::B_SIGNED] = 0;
eq_cell->setPort(ID::A, gold_masked);
eq_cell->setPort(ID::B, gate_masked);
eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
eq_cell->setPort(ID::Y, miter_module->addWire(NEWER_ID));
this_condition = eq_cell->getPort(ID::Y);
}
else
{
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx));
RTLIL::Cell *eq_cell = miter_module->addCell(NEWER_ID, ID($eqx));
eq_cell->parameters[ID::A_WIDTH] = w_gold->width;
eq_cell->parameters[ID::B_WIDTH] = w_gate->width;
eq_cell->parameters[ID::Y_WIDTH] = 1;
@ -238,7 +238,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
eq_cell->parameters[ID::B_SIGNED] = 0;
eq_cell->setPort(ID::A, w_gold);
eq_cell->setPort(ID::B, w_gate);
eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
eq_cell->setPort(ID::Y, miter_module->addWire(NEWER_ID));
this_condition = eq_cell->getPort(ID::Y);
}
@ -251,7 +251,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (flag_make_cover)
{
auto cover_condition = miter_module->Not(NEW_ID, this_condition);
auto cover_condition = miter_module->Not(NEWER_ID, this_condition);
miter_module->addCover("\\cover_" + RTLIL::unescape_id(gold_wire->name), cover_condition, State::S1);
}
@ -260,17 +260,17 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
}
if (all_conditions.size() != 1) {
RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, ID($reduce_and));
RTLIL::Cell *reduce_cell = miter_module->addCell(NEWER_ID, ID($reduce_and));
reduce_cell->parameters[ID::A_WIDTH] = all_conditions.size();
reduce_cell->parameters[ID::Y_WIDTH] = 1;
reduce_cell->parameters[ID::A_SIGNED] = 0;
reduce_cell->setPort(ID::A, all_conditions);
reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
reduce_cell->setPort(ID::Y, miter_module->addWire(NEWER_ID));
all_conditions = reduce_cell->getPort(ID::Y);
}
if (flag_make_assert) {
RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, ID($assert));
RTLIL::Cell *assert_cell = miter_module->addCell(NEWER_ID, ID($assert));
assert_cell->setPort(ID::A, all_conditions);
assert_cell->setPort(ID::EN, State::S1);
}
@ -278,7 +278,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
RTLIL::Wire *w_trigger = miter_module->addWire(ID(trigger));
w_trigger->port_output = true;
RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, ID($not));
RTLIL::Cell *not_cell = miter_module->addCell(NEWER_ID, ID($not));
not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
not_cell->parameters[ID::Y_WIDTH] = w_trigger->width;
@ -355,13 +355,13 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
if (!cell->type.in(ID($assert), ID($assume)))
continue;
SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1);
SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(ID::EN), State::S1);
SigBit is_active = module->Nex(NEWER_ID, cell->getPort(ID::A), State::S1);
SigBit is_enabled = module->Eqx(NEWER_ID, cell->getPort(ID::EN), State::S1);
if (cell->type == ID($assert)) {
assert_signals.append(module->And(NEW_ID, is_active, is_enabled));
assert_signals.append(module->And(NEWER_ID, is_active, is_enabled));
} else {
assume_signals.append(module->And(NEW_ID, is_active, is_enabled));
assume_signals.append(module->And(NEWER_ID, is_active, is_enabled));
}
module->remove(cell);
@ -369,20 +369,20 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
if (assume_signals.empty())
{
module->addReduceOr(NEW_ID, assert_signals, trigger);
module->addReduceOr(NEWER_ID, assert_signals, trigger);
}
else
{
Wire *assume_q = module->addWire(NEW_ID);
Wire *assume_q = module->addWire(NEWER_ID);
assume_q->attributes[ID::init] = State::S0;
assume_signals.append(assume_q);
SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals);
SigSpec assume_ok = module->Not(NEW_ID, assume_nok);
module->addFf(NEW_ID, assume_nok, assume_q);
SigSpec assume_nok = module->ReduceOr(NEWER_ID, assume_signals);
SigSpec assume_ok = module->Not(NEWER_ID, assume_nok);
module->addFf(NEWER_ID, assume_nok, assume_q);
SigSpec assert_fail = module->ReduceOr(NEW_ID, assert_signals);
module->addAnd(NEW_ID, assert_fail, assume_ok, trigger);
SigSpec assert_fail = module->ReduceOr(NEWER_ID, assert_signals);
module->addAnd(NEWER_ID, assert_fail, assume_ok, trigger);
}
if (flag_flatten) {

18
passes/sat/mutate.cc
View file

@ -629,7 +629,7 @@ SigBit mutate_ctrl(Module *module, const mutate_opts_t &opts)
return State::S1;
SigSpec sig = mutate_ctrl_sig(module, opts.ctrl_name, opts.ctrl_width);
return module->Eq(NEW_ID, sig, Const(opts.ctrl_value, GetSize(sig)));
return module->Eq(NEWER_ID, sig, Const(opts.ctrl_value, GetSize(sig)));
}
SigSpec mutate_ctrl_mux(Module *module, const mutate_opts_t &opts, SigSpec unchanged_sig, SigSpec changed_sig)
@ -639,7 +639,7 @@ SigSpec mutate_ctrl_mux(Module *module, const mutate_opts_t &opts, SigSpec uncha
return unchanged_sig;
if (ctrl_bit == State::S1)
return changed_sig;
return module->Mux(NEW_ID, unchanged_sig, changed_sig, ctrl_bit);
return module->Mux(NEWER_ID, unchanged_sig, changed_sig, ctrl_bit);
}
void mutate_inv(Design *design, const mutate_opts_t &opts)
@ -653,14 +653,14 @@ void mutate_inv(Design *design, const mutate_opts_t &opts)
if (cell->input(opts.port))
{
log("Add input inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
SigBit outbit = module->Not(NEW_ID, bit);
SigBit outbit = module->Not(NEWER_ID, bit);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = module->Not(NEW_ID, inbit);
SigBit inbit = module->addWire(NEWER_ID);
SigBit outbit = module->Not(NEWER_ID, inbit);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
bit = inbit;
}
@ -687,7 +687,7 @@ void mutate_const(Design *design, const mutate_opts_t &opts, bool one)
else
{
log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit inbit = module->addWire(NEWER_ID);
SigBit outbit = one ? State::S1 : State::S0;
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
bit = inbit;
@ -710,14 +710,14 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
if (cell->input(opts.port))
{
log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit);
SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_ID, bit, ctrl);
SigBit outbit = one ? module->Xor(NEWER_ID, bit, ctrl) : module->Xnor(NEWER_ID, bit, ctrl);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_ID, inbit, ctrl);
SigBit inbit = module->addWire(NEWER_ID);
SigBit outbit = one ? module->Xor(NEWER_ID, inbit, ctrl) : module->Xnor(NEWER_ID, inbit, ctrl);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
bit = inbit;
}

4
passes/sat/qbfsat.cc
View file

@ -312,8 +312,8 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
if (cur_thresh != 0) {
//Add thresholding logic (but not on the initial run when we don't have a sense of where to start):
RTLIL::SigSpec comparator = maximize? module->Ge(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false)
: module->Le(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false);
RTLIL::SigSpec comparator = maximize? module->Ge(NEWER_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false)
: module->Le(NEWER_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false);
module->addAssume(wire_to_optimize_name.str() + "__threshold", comparator, RTLIL::Const(1, 1));
log("Trying to solve with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), cur_thresh);

2
passes/sat/recover_names.cc
View file

@ -95,7 +95,7 @@ struct RecoverModuleWorker {
{
// Create a derivative of the module with whiteboxes flattened so we can
// run eval and sat on it
flat = design->addModule(NEW_ID);
flat = design->addModule(NEWER_ID);
mod->cloneInto(flat);
Pass::call_on_module(design, flat, "flatten -wb");
ce = new ConstEval(flat);

6
passes/sat/supercover.cc
View file

@ -78,9 +78,9 @@ struct SupercoverPass : public Pass {
if (handled_bits.count(bit))
continue;
SigSpec inv = module->Not(NEW_ID, bit);
module->addCover(NEW_ID, bit, State::S1, src);
module->addCover(NEW_ID, inv, State::S1, src);
SigSpec inv = module->Not(NEWER_ID, bit);
module->addCover(NEWER_ID, bit, State::S1, src);
module->addCover(NEWER_ID, inv, State::S1, src);
handled_bits.insert(bit);
if (!counted_wire) {

18
passes/sat/synthprop.cc
View file

@ -107,16 +107,16 @@ void SynthPropWorker::run()
int num = 0;
RTLIL::Wire *port_wire = data.first->wire(port_name);
if (!reset_name.empty() && data.first == module) {
port_wire = data.first->addWire(NEW_ID, data.second.names.size());
port_wire = data.first->addWire(NEWER_ID, data.second.names.size());
output = port_wire;
}
pool<Wire*> connected;
for (auto cell : data.second.assertion_cells) {
if (cell->type == ID($assert)) {
RTLIL::Wire *neg_wire = data.first->addWire(NEW_ID);
RTLIL::Wire *result_wire = data.first->addWire(NEW_ID);
data.first->addNot(NEW_ID, cell->getPort(ID::A), neg_wire);
data.first->addAnd(NEW_ID, cell->getPort(ID::EN), neg_wire, result_wire);
RTLIL::Wire *neg_wire = data.first->addWire(NEWER_ID);
RTLIL::Wire *result_wire = data.first->addWire(NEWER_ID);
data.first->addNot(NEWER_ID, cell->getPort(ID::A), neg_wire);
data.first->addAnd(NEWER_ID, cell->getPort(ID::EN), neg_wire, result_wire);
if (!or_outputs) {
data.first->connect(SigBit(port_wire,num), result_wire);
} else {
@ -132,7 +132,7 @@ void SynthPropWorker::run()
if (!or_outputs) {
cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size()));
} else {
RTLIL::Wire *result_wire = data.first->addWire(NEW_ID);
RTLIL::Wire *result_wire = data.first->addWire(NEWER_ID);
cell->setPort(port_name, result_wire);
connected.emplace(result_wire);
}
@ -146,8 +146,8 @@ void SynthPropWorker::run()
if (!prev_wire) {
prev_wire = wire;
} else {
RTLIL::Wire *result = data.first->addWire(NEW_ID);
data.first->addOr(NEW_ID, prev_wire, wire, result);
RTLIL::Wire *result = data.first->addWire(NEWER_ID);
data.first->addOr(NEWER_ID, prev_wire, wire, result);
prev_wire = result;
}
}
@ -163,7 +163,7 @@ void SynthPropWorker::run()
SigSpec reset = module->wire(reset_name);
reset.extend_u0(width, true);
module->addDlatchsr(NEW_ID, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol);
module->addDlatchsr(NEWER_ID, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol);
}
if (!map_file.empty()) {

24
passes/techmap/abc9_ops.cc
View file

@ -344,7 +344,7 @@ void prep_bypass(RTLIL::Design *design)
// For these new input ports driven by the replaced
// cell, then create a new simple-path specify entry:
// (input => output) = 0
auto specify = bypass_module->addCell(NEW_ID, ID($specify2));
auto specify = bypass_module->addCell(NEWER_ID, ID($specify2));
specify->setPort(ID::EN, State::S1);
specify->setPort(ID::SRC, src);
specify->setPort(ID::DST, dst);
@ -405,7 +405,7 @@ void prep_bypass(RTLIL::Design *design)
}
sig = std::move(new_sig);
};
auto specify = bypass_module->addCell(NEW_ID, cell);
auto specify = bypass_module->addCell(NEWER_ID, cell);
specify->rewrite_sigspecs(rw);
}
bypass_module->fixup_ports();
@ -415,7 +415,7 @@ void prep_bypass(RTLIL::Design *design)
// original cell, but with additional inputs taken from the
// replaced cell
auto replace_cell = map_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
auto bypass_cell = map_module->addCell(NEW_ID, cell->type.str() + "_$abc9_byp");
auto bypass_cell = map_module->addCell(NEWER_ID, cell->type.str() + "_$abc9_byp");
for (const auto &conn : cell->connections()) {
auto port = map_module->wire(conn.first);
if (cell->input(conn.first)) {
@ -503,8 +503,8 @@ void prep_dff_submod(RTLIL::Design *design)
// Add an always-enabled CE mux that drives $_DFF_[NP]_.D so that:
// (a) flop box will have an output
// (b) $_DFF_[NP]_.Q will be present as an input
SigBit D = module->addWire(NEW_ID);
module->addMuxGate(NEW_ID, dff_cell->getPort(ID::D), Q, State::S0, D);
SigBit D = module->addWire(NEWER_ID);
module->addMuxGate(NEWER_ID, dff_cell->getPort(ID::D), Q, State::S0, D);
dff_cell->setPort(ID::D, D);
// Rewrite $specify cells that end with $_DFF_[NP]_.Q
@ -592,7 +592,7 @@ void break_scc(RTLIL::Module *module)
for (auto &c : cell->connections_) {
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
Wire *w = module->addWire(NEWER_ID, GetSize(c.second));
I.append(w);
O.append(c.second);
c.second = w;
@ -602,7 +602,7 @@ void break_scc(RTLIL::Module *module)
if (!I.empty())
{
auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER));
auto cell = module->addCell(NEWER_ID, ID($__ABC9_SCC_BREAKER));
log_assert(GetSize(I) == GetSize(O));
cell->setParam(ID::WIDTH, GetSize(I));
cell->setPort(ID::I, std::move(I));
@ -680,7 +680,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
auto rhs = cell->getPort(i.first.name);
if (offset >= rhs.size())
continue;
auto O = module->addWire(NEW_ID);
auto O = module->addWire(NEWER_ID);
#ifndef NDEBUG
if (ys_debug(1)) {
@ -694,7 +694,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
r.first->second = delay_module->derive(design, {{ID::DELAY, d}});
log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
}
auto box = module->addCell(NEW_ID, r.first->second);
auto box = module->addCell(NEWER_ID, r.first->second);
box->setPort(ID::I, rhs[offset]);
box->setPort(ID::O, O);
rhs[offset] = O;
@ -831,7 +831,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
auto &holes_cell = r.first->second;
if (r.second) {
if (box_module->get_bool_attribute(ID::whitebox)) {
holes_cell = holes_module->addCell(NEW_ID, cell->type);
holes_cell = holes_module->addCell(NEWER_ID, cell->type);
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc -noopt");
@ -1256,7 +1256,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
bit_drivers[y_bit].insert(mapped_cell->name);
if (!a_bit.wire) {
mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
mapped_cell->setPort(ID::Y, module->addWire(NEWER_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@ -1549,7 +1549,7 @@ clone_lut:
if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}
auto cell = module->addLut(NEW_ID,
auto cell = module->addLut(NEWER_ID,
driver_lut->getPort(ID::A),
y_bit,
driver_mask);

12
passes/techmap/aigmap.cc
View file

@ -108,8 +108,8 @@ struct AigmapPass : public Pass {
SigBit A = sigs.at(node.left_parent);
SigBit B = sigs.at(node.right_parent);
if (nand_mode && node.inverter) {
bit = module->addWire(NEW_ID);
auto gate = module->addNandGate(NEW_ID, A, B, bit);
bit = module->addWire(NEWER_ID);
auto gate = module->addNandGate(NEWER_ID, A, B, bit);
if (select_mode)
new_sel.insert(gate->name);
@ -119,8 +119,8 @@ struct AigmapPass : public Pass {
if (and_cache.count(key))
bit = and_cache.at(key);
else {
bit = module->addWire(NEW_ID);
auto gate = module->addAndGate(NEW_ID, A, B, bit);
bit = module->addWire(NEWER_ID);
auto gate = module->addAndGate(NEWER_ID, A, B, bit);
if (select_mode)
new_sel.insert(gate->name);
}
@ -128,8 +128,8 @@ struct AigmapPass : public Pass {
}
if (node.inverter) {
SigBit new_bit = module->addWire(NEW_ID);
auto gate = module->addNotGate(NEW_ID, bit, new_bit);
SigBit new_bit = module->addWire(NEWER_ID);
auto gate = module->addNotGate(NEWER_ID, bit, new_bit);
bit = new_bit;
if (select_mode)
new_sel.insert(gate->name);

28
passes/techmap/alumacc.cc
View file

@ -52,7 +52,7 @@ struct AlumaccWorker
if (is_signed) {
get_of();
get_sf();
cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
cached_lt = alu_cell->module->Xor(NEWER_ID, cached_of, cached_sf);
}
else
cached_lt = get_cf();
@ -64,21 +64,21 @@ struct AlumaccWorker
if (GetSize(cached_gt) == 0) {
get_lt();
get_eq();
SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
SigSpec Or = alu_cell->module->Or(NEWER_ID, cached_lt, cached_eq);
cached_gt = alu_cell->module->Not(NEWER_ID, Or, false, alu_cell->get_src_attribute());
}
return cached_gt;
}
RTLIL::SigSpec get_eq() {
if (GetSize(cached_eq) == 0)
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute());
cached_eq = alu_cell->module->ReduceAnd(NEWER_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute());
return cached_eq;
}
RTLIL::SigSpec get_ne() {
if (GetSize(cached_ne) == 0)
cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->get_src_attribute());
cached_ne = alu_cell->module->Not(NEWER_ID, get_eq(), false, alu_cell->get_src_attribute());
return cached_ne;
}
@ -86,7 +86,7 @@ struct AlumaccWorker
if (GetSize(cached_cf) == 0) {
cached_cf = alu_cell->getPort(ID::CO);
log_assert(GetSize(cached_cf) >= 1);
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
cached_cf = alu_cell->module->Not(NEWER_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
}
return cached_cf;
}
@ -95,7 +95,7 @@ struct AlumaccWorker
if (GetSize(cached_of) == 0) {
cached_of = {alu_cell->getPort(ID::CO), alu_cell->getPort(ID::CI)};
log_assert(GetSize(cached_of) >= 2);
cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
cached_of = alu_cell->module->Xor(NEWER_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
}
return cached_of;
}
@ -362,7 +362,7 @@ struct AlumaccWorker
for (auto &it : sig_macc)
{
auto n = it.second;
auto cell = module->addCell(NEW_ID, ID($macc));
auto cell = module->addCell(NEWER_ID, ID($macc));
macc_counter++;
@ -428,7 +428,7 @@ struct AlumaccWorker
n->a = A;
n->b = B;
n->c = State::S1;
n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
n->y = module->addWire(NEWER_ID, max(GetSize(A), GetSize(B)));
n->is_signed = is_signed;
n->invert_b = true;
sig_alu[RTLIL::SigSig(A, B)].insert(n);
@ -482,7 +482,7 @@ struct AlumaccWorker
{
if (GetSize(n->b) == 0 && GetSize(n->c) == 0 && GetSize(n->cmp) == 0)
{
n->alu_cell = module->addPos(NEW_ID, n->a, n->y, n->is_signed);
n->alu_cell = module->addPos(NEWER_ID, n->a, n->y, n->is_signed);
log(" creating $pos cell for ");
for (int i = 0; i < GetSize(n->cells); i++)
@ -492,7 +492,7 @@ struct AlumaccWorker
goto delete_node;
}
n->alu_cell = module->addCell(NEW_ID, ID($alu));
n->alu_cell = module->addCell(NEWER_ID, ID($alu));
alu_counter++;
log(" creating $alu cell for ");
@ -508,8 +508,8 @@ struct AlumaccWorker
n->alu_cell->setPort(ID::CI, GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort(ID::BI, n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort(ID::Y, n->y);
n->alu_cell->setPort(ID::X, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::X, module->addWire(NEWER_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::CO, module->addWire(NEWER_ID, GetSize(n->y)));
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
for (auto &it : n->cmp)
@ -527,7 +527,7 @@ struct AlumaccWorker
if (cmp_ne) sig.append(n->get_ne());
if (GetSize(sig) > 1)
sig = module->ReduceOr(NEW_ID, sig);
sig = module->ReduceOr(NEWER_ID, sig);
sig.extend_u0(GetSize(cmp_y));
module->connect(cmp_y, sig);

12
passes/techmap/bmuxmap.cc
View file

@ -68,22 +68,22 @@ struct BmuxmapPass : public Pass {
{
int num_cases = 1 << s_width;
SigSpec new_a = SigSpec(State::Sx, width);
SigSpec new_s = module->addWire(NEW_ID, num_cases);
SigSpec new_data = module->addWire(NEW_ID, width);
SigSpec new_s = module->addWire(NEWER_ID, num_cases);
SigSpec new_data = module->addWire(NEWER_ID, width);
for (int val = 0; val < num_cases; val++)
{
module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]);
module->addEq(NEWER_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]);
}
RTLIL::Cell *pmux = module->addPmux(NEW_ID, new_a, data, new_s, new_data);
RTLIL::Cell *pmux = module->addPmux(NEWER_ID, new_a, data, new_s, new_data);
pmux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
data = new_data;
}
else
{
for (int idx = 0; idx < GetSize(sel); idx++) {
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
SigSpec new_data = module->addWire(NEWER_ID, GetSize(data)/2);
for (int i = 0; i < GetSize(new_data); i += width) {
RTLIL::Cell *mux = module->addMux(NEW_ID,
RTLIL::Cell *mux = module->addMux(NEWER_ID,
data.extract(i*2, width),
data.extract(i*2+width, width),
sel[idx],

152
passes/techmap/booth.cc
View file

@ -75,44 +75,44 @@ struct BoothPassWorker {
// Booth unsigned decoder lsb
SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i)
{
SigBit and_op = module->AndGate(NEW_ID_SUFFIX(name), lsb_i, one_i);
return module->XorGate(NEW_ID_SUFFIX(name), and_op, s_i);
SigBit and_op = module->AndGate(NEWER_ID_SUFFIX(name), lsb_i, one_i);
return module->XorGate(NEWER_ID_SUFFIX(name), and_op, s_i);
}
// Booth unsigned radix4 decoder
SigBit Bur4d_n(std::string name, SigBit yn_i, SigBit ynm1_i, SigBit one_i, SigBit two_i, SigBit s_i)
{
// ppij = ((yn & one) | (ynm1 & two)) ^ s;
SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), yn_i, one_i);
SigBit an2 = module->AndGate(NEW_ID_SUFFIX(name), ynm1_i, two_i);
SigBit or1 = module->OrGate(NEW_ID_SUFFIX(name), an1, an2);
return module->XorGate(NEW_ID_SUFFIX(name), s_i, or1);
SigBit an1 = module->AndGate(NEWER_ID_SUFFIX(name), yn_i, one_i);
SigBit an2 = module->AndGate(NEWER_ID_SUFFIX(name), ynm1_i, two_i);
SigBit or1 = module->OrGate(NEWER_ID_SUFFIX(name), an1, an2);
return module->XorGate(NEWER_ID_SUFFIX(name), s_i, or1);
}
// Booth unsigned radix4 decoder
SigBit Bur4d_msb(std::string name, SigBit msb_i, SigBit two_i, SigBit s_i)
{
// ppij = (msb & two) ^ s;
SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), msb_i, two_i);
return module->XorGate(NEW_ID_SUFFIX(name), s_i, an1);
SigBit an1 = module->AndGate(NEWER_ID_SUFFIX(name), msb_i, two_i);
return module->XorGate(NEWER_ID_SUFFIX(name), s_i, an1);
}
// half adder, used in CPA
void BuildHa(std::string name, SigBit a_i, SigBit b_i, SigBit &s_o, SigBit &c_o)
{
s_o = module->XorGate(NEW_ID_SUFFIX(name), a_i, b_i);
c_o = module->AndGate(NEW_ID_SUFFIX(name), a_i, b_i);
s_o = module->XorGate(NEWER_ID_SUFFIX(name), a_i, b_i);
c_o = module->AndGate(NEWER_ID_SUFFIX(name), a_i, b_i);
}
// Booth unsigned radix 4 encoder
void BuildBur4e(std::string name, SigBit y0_i, SigBit y1_i, SigBit y2_i,
SigBit &one_o, SigBit &two_o, SigBit &s_o, SigBit &sb_o)
{
one_o = module->XorGate(NEW_ID_SUFFIX(name), y0_i, y1_i);
one_o = module->XorGate(NEWER_ID_SUFFIX(name), y0_i, y1_i);
s_o = y2_i;
sb_o = module->NotGate(NEW_ID_SUFFIX(name), y2_i);
SigBit y1_xnor_y2 = module->XnorGate(NEW_ID_SUFFIX(name), y1_i, y2_i);
two_o = module->NorGate(NEW_ID_SUFFIX(name), y1_xnor_y2, one_o);
sb_o = module->NotGate(NEWER_ID_SUFFIX(name), y2_i);
SigBit y1_xnor_y2 = module->XnorGate(NEWER_ID_SUFFIX(name), y1_i, y2_i);
two_o = module->NorGate(NEWER_ID_SUFFIX(name), y1_xnor_y2, one_o);
}
void BuildBr4e(std::string name, SigBit y2_m1_i,
@ -120,9 +120,9 @@ struct BoothPassWorker {
SigBit y2_p1_i,
SigBit &negi_o, SigBit &twoi_n_o, SigBit &onei_n_o, SigBit &cori_o)
{
auto y2_p1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_p1_i);
auto y2_n = module->NotGate(NEW_ID_SUFFIX(name), y2_i);
auto y2_m1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_m1_i);
auto y2_p1_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_p1_i);
auto y2_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_i);
auto y2_m1_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_m1_i);
negi_o = y2_p1_i;
@ -130,15 +130,15 @@ struct BoothPassWorker {
// (y2_p1_n & y2_i & y2_m1_i) |
// (y2_p1 & y2_n & y2_m1_n)
// )
twoi_n_o = module->NorGate(NEW_ID_SUFFIX(name),
module->AndGate(NEW_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEW_ID_SUFFIX(name), y2_i, y2_m1_i)),
module->AndGate(NEW_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEW_ID_SUFFIX(name), y2_n, y2_m1_n))
twoi_n_o = module->NorGate(NEWER_ID_SUFFIX(name),
module->AndGate(NEWER_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEWER_ID_SUFFIX(name), y2_i, y2_m1_i)),
module->AndGate(NEWER_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEWER_ID_SUFFIX(name), y2_n, y2_m1_n))
);
// onei_n = ~(y2_m1_i ^ y2_i);
onei_n_o = module->XnorGate(NEW_ID_SUFFIX(name), y2_m1_i, y2_i);
onei_n_o = module->XnorGate(NEWER_ID_SUFFIX(name), y2_m1_i, y2_i);
// cori = (y2_m1_n | y2_n) & y2_p1_i;
cori_o = module->AndGate(NEW_ID_SUFFIX(name), module->OrGate(NEW_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i);
cori_o = module->AndGate(NEWER_ID_SUFFIX(name), module->OrGate(NEWER_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i);
}
//
@ -150,10 +150,10 @@ struct BoothPassWorker {
// nxj_in = xnor(xj,negi)
// nxj_o = xnj_in,
// ppij = ~( (nxj_m1_i | twoi_n_i) & (nxj_int | onei_n_i));
nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), xj_i, negi_i);
ppij_o = module->NandGate(NEW_ID_SUFFIX(name),
module->OrGate(NEW_ID_SUFFIX(name), nxj_m1_i, twoi_n_i),
module->OrGate(NEW_ID_SUFFIX(name), nxj_o, onei_n_i)
nxj_o = module->XnorGate(NEWER_ID_SUFFIX(name), xj_i, negi_i);
ppij_o = module->NandGate(NEWER_ID_SUFFIX(name),
module->OrGate(NEWER_ID_SUFFIX(name), nxj_m1_i, twoi_n_i),
module->OrGate(NEWER_ID_SUFFIX(name), nxj_o, onei_n_i)
);
}
@ -177,14 +177,14 @@ struct BoothPassWorker {
//correction propagation
assign CORO = (~PP1 & ~PP0)? CORI : 1'b0;
*/
nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), x1_i, negi_i);
pp0_o = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y0_i);
SigBit pp1_1_int = module->AndGate(NEW_ID_SUFFIX(name), x1_i, y0_i);
SigBit pp1_2_int = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y1_i);
pp1_o = module->XorGate(NEW_ID_SUFFIX(name), pp1_1_int, pp1_2_int);
nxj_o = module->XnorGate(NEWER_ID_SUFFIX(name), x1_i, negi_i);
pp0_o = module->AndGate(NEWER_ID_SUFFIX(name), x0_i, y0_i);
SigBit pp1_1_int = module->AndGate(NEWER_ID_SUFFIX(name), x1_i, y0_i);
SigBit pp1_2_int = module->AndGate(NEWER_ID_SUFFIX(name), x0_i, y1_i);
pp1_o = module->XorGate(NEWER_ID_SUFFIX(name), pp1_1_int, pp1_2_int);
SigBit pp1_nor_pp0 = module->NorGate(NEW_ID_SUFFIX(name), pp1_o, pp0_o);
cor_o = module->AndGate(NEW_ID_SUFFIX(name), pp1_nor_pp0, cori_i);
SigBit pp1_nor_pp0 = module->NorGate(NEWER_ID_SUFFIX(name), pp1_o, pp0_o);
cor_o = module->AndGate(NEWER_ID_SUFFIX(name), pp1_nor_pp0, cori_i);
}
void BuildBitwiseFa(Module *mod, std::string name, const SigSpec &sig_a, const SigSpec &sig_b,
@ -289,7 +289,7 @@ struct BoothPassWorker {
int required_op_size = x_sz_revised + y_sz_revised;
if (required_op_size != z_sz) {
SigSpec expanded_Y = module->addWire(NEW_ID, required_op_size);
SigSpec expanded_Y = module->addWire(NEWER_ID, required_op_size);
SigSpec Y_driver = expanded_Y;
Y_driver.extend_u0(Y.size(), is_signed);
module->connect(Y, Y_driver);
@ -326,9 +326,9 @@ struct BoothPassWorker {
std::vector<SigSpec> new_summands;
int i;
for (i = 0; i < (int) summands.size() - 2; i += 3) {
SigSpec x = module->addWire(NEW_ID, width);
SigSpec y = module->addWire(NEW_ID, width);
BuildBitwiseFa(module, NEW_ID.str(), summands[i], summands[i + 1],
SigSpec x = module->addWire(NEWER_ID, width);
SigSpec y = module->addWire(NEWER_ID, width);
BuildBitwiseFa(module, NEWER_ID.str(), summands[i], summands[i + 1],
summands[i + 2], x, y);
new_summands.push_back(y);
new_summands.push_back({x.extract(0, width - 1), State::S0});
@ -424,7 +424,7 @@ struct BoothPassWorker {
if (mapped_cpa)
BuildCPA(module, wtree_sum.first, {State::S0, wtree_sum.second.extract_end(1)}, Z);
else
module->addAdd(NEW_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z);
module->addAdd(NEWER_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z);
}
/*
@ -460,11 +460,11 @@ struct BoothPassWorker {
// append the sign bits
if (is_signed) {
SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int[0], one_int[0])));
ppij_vec.append({module->NotGate(NEW_ID, e), e, e});
SigBit e = module->XorGate(NEWER_ID, s_int[0], module->AndGate(NEWER_ID, X.msb(), module->OrGate(NEWER_ID, two_int[0], one_int[0])));
ppij_vec.append({module->NotGate(NEWER_ID, e), e, e});
} else {
// append the sign bits
ppij_vec.append({module->NotGate(NEW_ID, s_int[0]), s_int[0], s_int[0]});
ppij_vec.append({module->NotGate(NEWER_ID, s_int[0]), s_int[0], s_int[0]});
}
}
@ -494,7 +494,7 @@ struct BoothPassWorker {
one_int, two_int, s_int));
}
ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int, one_int))));
ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEWER_ID, sb_int, module->AndGate(NEWER_ID, X.msb(), module->OrGate(NEWER_ID, two_int, one_int))));
ppij_vec.append(State::S1);
}
@ -721,7 +721,7 @@ struct BoothPassWorker {
// Base Case: Bit 0 is sum 0
if (n == 0) {
module->addBufGate(NEW_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]);
module->addBufGate(NEWER_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]);
#ifdef DEBUG_CPA
printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.c_str(), s_vec[0]->name.c_str());
@ -747,8 +747,8 @@ struct BoothPassWorker {
// End Case
else if (n == s_vec.size() - 1) {
// Make the carry results.. Two extra bits after fa.
SigBit carry_out = module->addWire(NEW_ID, 1);
module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
SigBit carry_out = module->addWire(NEWER_ID, 1);
module->addFa(NEWER_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
/* A */ s_vec[n],
/* B */ c_vec[n - 1],
/* C */ carry,
@ -775,8 +775,8 @@ struct BoothPassWorker {
}
// Step case
else {
SigBit carry_out = module->addWire(NEW_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1);
module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
SigBit carry_out = module->addWire(NEWER_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1);
module->addFa(NEWER_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
/* A */ s_vec[n],
/* B */ c_vec[n - 1],
/* C */ carry,
@ -814,10 +814,10 @@ struct BoothPassWorker {
if (first_csa_ips.size() > 0) {
// build the first csa
auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto s_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto c_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
auto csa = module->addFa(NEWER_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
/* A */ first_csa_ips[0],
/* B */ first_csa_ips.size() > 1 ? first_csa_ips[1] : State::S0,
/* C */ first_csa_ips.size() > 2 ? first_csa_ips[2] : State::S0,
@ -846,10 +846,10 @@ struct BoothPassWorker {
}
if (csa_ips.size() > 0) {
auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto c_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto s_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
auto csa = module->addFa(NEWER_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
/* A */ s_result,
/* B */ csa_ips[0],
/* C */ csa_ips.size() > 1 ? csa_ips[1] : State::S0,
@ -879,10 +879,10 @@ struct BoothPassWorker {
for (int y_ix = 0; y_ix < (!is_signed ? y_sz : y_sz - 1);) {
std::string enc_name = stringf("bur_enc_%d", encoder_ix);
two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
two_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
if (y_ix == 0) {
BuildBur4e(enc_name, State::S0, Y[y_ix],
@ -939,10 +939,10 @@ struct BoothPassWorker {
std::string enc_name = stringf("br_enc_pad_%d", encoder_ix);
two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
two_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
SigBit one_o_int, two_o_int, s_o_int, sb_o_int;
BuildBur4e(enc_name, Y[y_ix], State::S0,
@ -986,10 +986,10 @@ struct BoothPassWorker {
for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) {
std::string enc_name = stringf("enc_%d", encoder_ix);
negi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1);
twoi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1);
onei_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1);
cori_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1);
negi_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1);
twoi_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1);
onei_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1);
cori_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1);
if (encoder_ix == 1) {
BuildBr4e(enc_name, State::S0, Y[0], Y[1],
@ -1024,10 +1024,10 @@ struct BoothPassWorker {
for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) {
for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) {
PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] =
module->addWire(NEW_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1);
module->addWire(NEWER_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1);
nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] =
module->addWire(NEW_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "",
module->addWire(NEWER_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "",
encoder_ix, decoder_ix)), 1);
}
}
@ -1042,7 +1042,7 @@ struct BoothPassWorker {
if (encoder_ix == 1) {
// quadrant 1 optimization
} else {
module->addNotGate(NEW_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)),
module->addNotGate(NEWER_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)),
negi_n_int[encoder_ix - 1],
nxj[(encoder_ix - 1) * dec_count]
);
@ -1094,16 +1094,16 @@ struct BoothPassWorker {
std::vector<SigSpec> fa_carry;
for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) {
fa_sum.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count));
fa_carry.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count));
fa_sum.push_back(module->addWire(NEWER_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count));
fa_carry.push_back(module->addWire(NEWER_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count));
}
// full adder creation
// base case: 1st row: Inputs from decoders
// 1st row exception: two localized inverters due to sign extension structure
SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]);
SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]);
BuildBitwiseFa(module, NEW_ID_SUFFIX("fa_row_0").str(),
SigBit d08_inv = module->NotGate(NEWER_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]);
SigBit d18_inv = module->NotGate(NEWER_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]);
BuildBitwiseFa(module, NEWER_ID_SUFFIX("fa_row_0").str(),
/* A */ {State::S0, d08_inv, PPij[(0 * dec_count) + x_sz], PPij.extract((0 * dec_count) + 2, x_sz - 1)},
/* B */ {State::S1, d18_inv, PPij.extract((1 * dec_count), x_sz)},
/* C */ fa_carry[0].extract(1, x_sz + 2),
@ -1116,10 +1116,10 @@ struct BoothPassWorker {
// special because these are driven by a decoder and prior fa.
for (fa_row_ix = 1; fa_row_ix < fa_row_count; fa_row_ix++) {
// end two bits: sign extension
SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)),
SigBit d_inv = module->NotGate(NEWER_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)),
PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]);
BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(),
BuildBitwiseFa(module, NEWER_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(),
/* A */ {State::S0, fa_carry[fa_row_ix - 1][fa_count - 1], fa_sum[fa_row_ix - 1].extract(2, x_sz + 2)},
/* B */ {State::S1, d_inv, PPij.extract((fa_row_ix + 1) * dec_count, x_sz), State::S0, State::S0},
@ -1132,7 +1132,7 @@ struct BoothPassWorker {
// instantiate the cpa
SigSpec cpa_carry;
if (z_sz > fa_row_count * 2)
cpa_carry = module->addWire(NEW_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2);
cpa_carry = module->addWire(NEWER_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2);
// The end case where we pass the last two summands
// from prior row directly to product output

4
passes/techmap/bufnorm.cc
View file

@ -384,7 +384,7 @@ struct BufnormPass : public Pass {
it->second.sort(compare_wires_f);
w = *(it->second.begin());
} else {
w = module->addWire(NEW_ID, GetSize(conn.second));
w = module->addWire(NEWER_ID, GetSize(conn.second));
for (int i = 0; i < GetSize(w); i++)
sigmap.add(SigBit(w, i), keysig[i]);
}
@ -434,7 +434,7 @@ struct BufnormPass : public Pass {
return;
}
Cell *cell = module->addCell(NEW_ID, type);
Cell *cell = module->addCell(NEWER_ID, type);
added_buffers.insert(cell);
cell->setPort(ID::A, src);

8
passes/techmap/bwmuxmap.cc
View file

@ -57,10 +57,10 @@ struct BwmuxmapPass : public Pass {
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto not_s = module->Not(NEW_ID, sig_s);
auto masked_b = module->And(NEW_ID, sig_s, sig_b);
auto masked_a = module->And(NEW_ID, not_s, sig_a);
module->addOr(NEW_ID, masked_a, masked_b, sig_y);
auto not_s = module->Not(NEWER_ID, sig_s);
auto masked_b = module->And(NEWER_ID, sig_s, sig_b);
auto masked_a = module->And(NEWER_ID, not_s, sig_a);
module->addOr(NEWER_ID, masked_a, masked_b, sig_y);
module->remove(cell);
}

10
passes/techmap/clkbufmap.cc
View file

@ -258,21 +258,21 @@ struct ClkbufmapPass : public Pass {
bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
log("Inserting %s on %s.%s[%d].\n", buf_celltype, log_id(module), log_id(wire), i);
cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEW_ID);
cell = module->addCell(NEWER_ID, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEWER_ID);
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
}
if (is_input) {
log("Inserting %s on %s.%s[%d].\n", inpad_celltype, log_id(module), log_id(wire), i);
RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
RTLIL::Cell *cell2 = module->addCell(NEWER_ID, RTLIL::escape_id(inpad_celltype));
if (iwire) {
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
} else {
cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit);
cell = cell2;
}
iwire = module->addWire(NEW_ID);
iwire = module->addWire(NEWER_ID);
cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
}
if (iwire)
@ -291,7 +291,7 @@ struct ClkbufmapPass : public Pass {
if (!input_bits.empty()) {
// This is an input port and some buffers were inserted -- we need
// to create a new input wire and transfer attributes.
Wire *new_wire = module->addWire(NEW_ID, wire);
Wire *new_wire = module->addWire(NEWER_ID, wire);
for (int i = 0; i < wire->width; i++) {
SigBit wire_bit(wire, i);

6
passes/techmap/clockgate.cc
View file

@ -371,17 +371,17 @@ struct ClockgatePass : public Pass {
if (!matching_icg_desc)
continue;
Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name);
Cell* icg = module->addCell(NEWER_ID, matching_icg_desc->name);
icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit);
icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit);
gclk.new_net = module->addWire(NEW_ID);
gclk.new_net = module->addWire(NEWER_ID);
icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
// Tie low DFT ports like scan chain enable
for (auto port : matching_icg_desc->tie_lo_pins)
icg->setPort(port, Const(0, 1));
// Fix CE polarity if needed
if (!clk.pol_ce) {
SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit);
SigBit ce_fixed_pol = module->NotGate(NEWER_ID, clk.ce_bit);
icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol);
}
}

4
passes/techmap/constmap.cc
View file

@ -32,8 +32,8 @@ static RTLIL::SigChunk value;
void constmap_worker(RTLIL::SigSpec &sig)
{
if (sig.is_fully_const()){
value = module->addWire(NEW_ID, sig.size());
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
value = module->addWire(NEWER_ID, sig.size());
RTLIL::Cell *cell = module->addCell(NEWER_ID, celltype);
cell->setParam(cell_paramname, sig.as_const());
cell->setPort(cell_portname, value);
sig = value;

8
passes/techmap/demuxmap.cc
View file

@ -57,13 +57,13 @@ struct DemuxmapPass : public Pass {
for (int i = 0; i < 1 << GetSize(sel); i++) {
if (width == 1 && data == State::S1) {
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), out[i]);
RTLIL::Cell *eq_cell = module->addEq(NEWER_ID, sel, Const(i, GetSize(sel)), out[i]);
eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
} else {
Wire *eq = module->addWire(NEW_ID);
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), eq);
Wire *eq = module->addWire(NEWER_ID);
RTLIL::Cell *eq_cell = module->addEq(NEWER_ID, sel, Const(i, GetSize(sel)), eq);
eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
RTLIL::Cell *mux = module->addMux(NEW_ID,
RTLIL::Cell *mux = module->addMux(NEWER_ID,
Const(State::S0, width),
data,
eq,

42
passes/techmap/dfflegalize.cc
View file

@ -280,7 +280,7 @@ struct DffLegalizePass : public Pass {
void emulate_split_init_arst(FfData &ff) {
ff.remove();
FfData ff_dff(ff.module, &initvals, NEW_ID);
FfData ff_dff(ff.module, &initvals, NEWER_ID);
ff_dff.width = ff.width;
ff_dff.has_aload = ff.has_aload;
ff_dff.sig_aload = ff.sig_aload;
@ -293,11 +293,11 @@ struct DffLegalizePass : public Pass {
ff_dff.has_ce = ff.has_ce;
ff_dff.sig_ce = ff.sig_ce;
ff_dff.pol_ce = ff.pol_ce;
ff_dff.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_dff.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_dff.val_init = ff.val_init;
ff_dff.is_fine = ff.is_fine;
FfData ff_adff(ff.module, &initvals, NEW_ID);
FfData ff_adff(ff.module, &initvals, NEWER_ID);
ff_adff.width = ff.width;
ff_adff.has_aload = ff.has_aload;
ff_adff.sig_aload = ff.sig_aload;
@ -310,7 +310,7 @@ struct DffLegalizePass : public Pass {
ff_adff.has_ce = ff.has_ce;
ff_adff.sig_ce = ff.sig_ce;
ff_adff.pol_ce = ff.pol_ce;
ff_adff.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_adff.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_adff.val_init = Const(State::Sx, ff.width);
ff_adff.has_arst = true;
ff_adff.sig_arst = ff.sig_arst;
@ -318,9 +318,9 @@ struct DffLegalizePass : public Pass {
ff_adff.val_arst = ff.val_arst;
ff_adff.is_fine = ff.is_fine;
FfData ff_sel(ff.module, &initvals, NEW_ID);
FfData ff_sel(ff.module, &initvals, NEWER_ID);
ff_sel.width = 1;
ff_sel.sig_q = ff.module->addWire(NEW_ID);
ff_sel.sig_q = ff.module->addWire(NEWER_ID);
ff_sel.has_arst = true;
ff_sel.sig_arst = ff.sig_arst;
ff_sel.pol_arst = ff.pol_arst;
@ -329,9 +329,9 @@ struct DffLegalizePass : public Pass {
ff_sel.is_fine = ff.is_fine;
if (ff.is_fine)
ff.module->addMuxGate(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMuxGate(NEWER_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
else
ff.module->addMux(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMux(NEWER_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
legalize_ff(ff_dff);
legalize_ff(ff_adff);
@ -386,7 +386,7 @@ struct DffLegalizePass : public Pass {
log_assert(ff.width == 1);
ff.remove();
FfData ff_clr(ff.module, &initvals, NEW_ID);
FfData ff_clr(ff.module, &initvals, NEWER_ID);
ff_clr.width = ff.width;
ff_clr.has_aload = ff.has_aload;
ff_clr.sig_aload = ff.sig_aload;
@ -403,11 +403,11 @@ struct DffLegalizePass : public Pass {
ff_clr.sig_arst = ff.sig_clr;
ff_clr.pol_arst = ff.pol_clr;
ff_clr.val_arst = Const(State::S0, ff.width);
ff_clr.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_clr.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_clr.val_init = init_clr ? ff.val_init : Const(State::Sx, ff.width);
ff_clr.is_fine = ff.is_fine;
FfData ff_set(ff.module, &initvals, NEW_ID);
FfData ff_set(ff.module, &initvals, NEWER_ID);
ff_set.width = ff.width;
ff_set.has_aload = ff.has_aload;
ff_set.sig_aload = ff.sig_aload;
@ -424,25 +424,25 @@ struct DffLegalizePass : public Pass {
ff_set.sig_arst = ff.sig_set;
ff_set.pol_arst = ff.pol_set;
ff_set.val_arst = Const(State::S1, ff.width);
ff_set.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_set.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_set.val_init = init_set ? ff.val_init : Const(State::Sx, ff.width);
ff_set.is_fine = ff.is_fine;
FfData ff_sel(ff.module, &initvals, NEW_ID);
FfData ff_sel(ff.module, &initvals, NEWER_ID);
ff_sel.width = ff.width;
ff_sel.has_sr = true;
ff_sel.pol_clr = ff.pol_clr;
ff_sel.pol_set = ff.pol_set;
ff_sel.sig_clr = ff.sig_clr;
ff_sel.sig_set = ff.sig_set;
ff_sel.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_sel.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_sel.val_init = Const(initsel, ff.width);
ff_sel.is_fine = ff.is_fine;
if (!ff.is_fine)
ff.module->addMux(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMux(NEWER_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
else
ff.module->addMuxGate(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMuxGate(NEWER_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
legalize_ff(ff_clr);
legalize_ff(ff_set);
@ -841,11 +841,11 @@ struct DffLegalizePass : public Pass {
ff.sig_ad = State::S0;
ff.val_arst = State::S1;
ff.remove_init();
Wire *new_q = ff.module->addWire(NEW_ID);
Wire *new_q = ff.module->addWire(NEWER_ID);
if (ff.is_fine)
ff.module->addNotGate(NEW_ID, new_q, ff.sig_q);
ff.module->addNotGate(NEWER_ID, new_q, ff.sig_q);
else
ff.module->addNot(NEW_ID, new_q, ff.sig_q);
ff.module->addNot(NEWER_ID, new_q, ff.sig_q);
ff.sig_q = new_q;
if (ff.val_init == State::S0)
ff.val_init = State::S1;
@ -938,9 +938,9 @@ struct DffLegalizePass : public Pass {
} else if (sig == State::S1) {
sig = State::S0;
} else if (ff.is_fine) {
sig = ff.module->NotGate(NEW_ID, sig);
sig = ff.module->NotGate(NEWER_ID, sig);
} else {
sig = ff.module->Not(NEW_ID, sig);
sig = ff.module->Not(NEWER_ID, sig);
}
pol = !pol;
}

10
passes/techmap/dfflibmap.cc
View file

@ -529,25 +529,25 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
} else
if (port.second == 'q') {
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->addWire(NEW_ID, GetSize(old_sig));
sig = module->addWire(NEWER_ID, GetSize(old_sig));
if (has_q && has_qn) {
for (auto &it : notmap[sigmap(old_sig)]) {
module->connect(it->getPort(ID::Y), sig);
it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig)));
it->setPort(ID::Y, module->addWire(NEWER_ID, GetSize(old_sig)));
}
} else {
module->addNotGate(NEW_ID, sig, old_sig);
module->addNotGate(NEWER_ID, sig, old_sig);
}
} else
if ('a' <= port.second && port.second <= 'z') {
sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->NotGate(NEW_ID, sig);
sig = module->NotGate(NEWER_ID, sig);
} else
if (port.second == '0' || port.second == '1') {
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
} else
if (port.second == 0) {
sig = module->addWire(NEW_ID);
sig = module->addWire(NEWER_ID);
} else
log_abort();
new_cell->setPort("\\" + port.first, sig);

8
passes/techmap/extract_counter.cc
View file

@ -639,8 +639,8 @@ void counter_worker(
//If the reset is active low, infer an inverter ($__COUNT_ cells always have active high reset)
if(extract.rst_inverted)
{
auto realreset = cell->module->addWire(NEW_ID);
cell->module->addNot(NEW_ID, extract.rst, RTLIL::SigSpec(realreset));
auto realreset = cell->module->addWire(NEWER_ID);
cell->module->addNot(NEWER_ID, extract.rst, RTLIL::SigSpec(realreset));
cell->setPort(ID(RST), realreset);
}
else
@ -665,8 +665,8 @@ void counter_worker(
cell->setParam(ID(HAS_CE), RTLIL::Const(1));
if(extract.ce_inverted)
{
auto realce = cell->module->addWire(NEW_ID);
cell->module->addNot(NEW_ID, extract.ce, RTLIL::SigSpec(realce));
auto realce = cell->module->addWire(NEWER_ID);
cell->module->addNot(NEWER_ID, extract.ce, RTLIL::SigSpec(realce));
cell->setPort(ID(CE), realce);
}
else

36
passes/techmap/extract_fa.cc
View file

@ -282,7 +282,7 @@ struct ExtractFaWorker
{
Cell *cell = driver.at(bit);
if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) {
cell->setPort(ID::Y, module->addWire(NEW_ID));
cell->setPort(ID::Y, module->addWire(NEWER_ID));
module->connect(bit, new_driver);
}
}
@ -394,17 +394,17 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
Cell *cell = module->addCell(NEWER_ID, ID($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEWER_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEWER_ID, B) : B);
cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEWER_ID, C) : C);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
X = module->addWire(NEWER_ID);
Y = module->addWire(NEWER_ID);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
@ -414,18 +414,18 @@ struct ExtractFaWorker
bool invert_y = f3i.inv_a ^ f3i.inv_b ^ f3i.inv_c;
if (func3.at(key).count(xor3_func)) {
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y;
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEWER_ID, Y) : Y;
for (auto bit : func3.at(key).at(xor3_func))
assign_new_driver(bit, YY);
}
if (func3.at(key).count(xnor3_func)) {
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y);
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEWER_ID, Y);
for (auto bit : func3.at(key).at(xnor3_func))
assign_new_driver(bit, YY);
}
SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEW_ID, X) : X;
SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEWER_ID, X) : X;
for (auto bit : func3.at(key).at(func))
assign_new_driver(bit, XX);
@ -501,35 +501,35 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
Cell *cell = module->addCell(NEWER_ID, ID($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEWER_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEWER_ID, B) : B);
cell->setPort(ID::C, State::S0);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
X = module->addWire(NEWER_ID);
Y = module->addWire(NEWER_ID);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
}
if (func2.at(key).count(xor2_func)) {
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y;
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEWER_ID, Y) : Y;
for (auto bit : func2.at(key).at(xor2_func))
assign_new_driver(bit, YY);
}
if (func2.at(key).count(xnor2_func)) {
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y);
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEWER_ID, Y);
for (auto bit : func2.at(key).at(xnor2_func))
assign_new_driver(bit, YY);
}
SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEW_ID, X) : X;
SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEWER_ID, X) : X;
for (auto bit : func2.at(key).at(func))
assign_new_driver(bit, XX);

6
passes/techmap/extract_reduce.cc
View file

@ -270,11 +270,11 @@ struct ExtractReducePass : public Pass
}
if (head_cell->type == ID($_AND_)) {
module->addReduceAnd(NEW_ID, input, output);
module->addReduceAnd(NEWER_ID, input, output);
} else if (head_cell->type == ID($_OR_)) {
module->addReduceOr(NEW_ID, input, output);
module->addReduceOr(NEWER_ID, input, output);
} else if (head_cell->type == ID($_XOR_)) {
module->addReduceXor(NEW_ID, input, output);
module->addReduceXor(NEWER_ID, input, output);
} else {
log_assert(false);
}

4
passes/techmap/extractinv.cc
View file

@ -105,10 +105,10 @@ struct ExtractinvPass : public Pass {
cell->parameters.erase(param_name);
if (invmask.is_fully_zero())
continue;
Wire *iwire = module->addWire(NEW_ID, sig.size());
Wire *iwire = module->addWire(NEWER_ID, sig.size());
for (int i = 0; i < sig.size(); i++)
if (invmask[i] == State::S1) {
RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
RTLIL::Cell *icell = module->addCell(NEWER_ID, RTLIL::escape_id(inv_celltype));
icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, log_id(module), log_id(cell->type), log_id(port.first), i);

4
passes/techmap/flowmap.cc
View file

@ -1411,7 +1411,7 @@ struct FlowmapWorker
if ((int)input_nodes.size() < minlut)
lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size()));
RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);
RTLIL::Cell *lut = module->addLut(NEWER_ID, lut_a, lut_y, lut_table);
mapped_nodes.insert(node);
for (auto gate_node : lut_gates[node])
{
@ -1432,7 +1432,7 @@ struct FlowmapWorker
{
auto origin = node_origins[node];
RTLIL::SigSpec driver = origin.cell->getPort(origin.port);
driver[origin.offset] = module->addWire(NEW_ID);
driver[origin.offset] = module->addWire(NEWER_ID);
origin.cell->setPort(origin.port, driver);
}
}

8
passes/techmap/hilomap.cc
View file

@ -36,16 +36,16 @@ void hilomap_worker(RTLIL::SigSpec &sig)
for (auto &bit : sig) {
if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi == RTLIL::State::Sm) {
last_hi = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
last_hi = module->addWire(NEWER_ID);
RTLIL::Cell *cell = module->addCell(NEWER_ID, RTLIL::escape_id(hicell_celltype));
cell->setPort(RTLIL::escape_id(hicell_portname), last_hi);
}
bit = last_hi;
}
if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
if (!singleton_mode || last_lo == RTLIL::State::Sm) {
last_lo = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
last_lo = module->addWire(NEWER_ID);
RTLIL::Cell *cell = module->addCell(NEWER_ID, RTLIL::escape_id(locell_celltype));
cell->setPort(RTLIL::escape_id(locell_portname), last_lo);
}
bit = last_lo;

2
passes/techmap/insbuf.cc
View file

@ -94,7 +94,7 @@ struct InsbufPass : public Pass {
sigmap.add(outbit);
}
Cell *cell = module->addCell(NEW_ID, celltype);
Cell *cell = module->addCell(NEWER_ID, celltype);
cell->setPort(in_portname, rhs);
cell->setPort(out_portname, lhs);

4
passes/techmap/iopadmap.cc
View file

@ -331,7 +331,7 @@ struct IopadmapPass : public Pass {
RTLIL::escape_id(tinoutpad_celltype));
if (tinoutpad_neg_oe)
en_sig = module->NotGate(NEW_ID, en_sig);
en_sig = module->NotGate(NEWER_ID, en_sig);
cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig);
cell->attributes[ID::keep] = RTLIL::Const(1);
@ -355,7 +355,7 @@ struct IopadmapPass : public Pass {
RTLIL::escape_id(toutpad_celltype));
if (toutpad_neg_oe)
en_sig = module->NotGate(NEW_ID, en_sig);
en_sig = module->NotGate(NEWER_ID, en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig);
cell->attributes[ID::keep] = RTLIL::Const(1);

12
passes/techmap/lut2mux.cc
View file

@ -32,22 +32,22 @@ int lut2mux(Cell *cell)
if (GetSize(sig_a) == 1)
{
cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
cell->module->addMuxGate(NEWER_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
}
else
{
SigSpec sig_a_hi = sig_a[GetSize(sig_a)-1];
SigSpec sig_a_lo = sig_a.extract(0, GetSize(sig_a)-1);
SigSpec sig_y1 = cell->module->addWire(NEW_ID);
SigSpec sig_y2 = cell->module->addWire(NEW_ID);
SigSpec sig_y1 = cell->module->addWire(NEWER_ID);
SigSpec sig_y2 = cell->module->addWire(NEWER_ID);
Const lut1 = lut.extract(0, GetSize(lut)/2);
Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2);
count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1));
count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2));
count += lut2mux(cell->module->addLut(NEWER_ID, sig_a_lo, sig_y1, lut1));
count += lut2mux(cell->module->addLut(NEWER_ID, sig_a_lo, sig_y2, lut2));
cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
cell->module->addMuxGate(NEWER_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
}
cell->module->remove(cell);

40
passes/techmap/maccmap.cc
View file

@ -52,7 +52,7 @@ struct MaccmapWorker
a.extend_u0(width, is_signed);
if (do_subtract) {
a = module->Not(NEW_ID, a);
a = module->Not(NEWER_ID, a);
add(State::S1, 0);
}
@ -73,13 +73,13 @@ struct MaccmapWorker
for (int i = 0; i < GetSize(b); i++)
if (is_signed && i+1 == GetSize(b))
{
a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)};
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
a = {module->Not(NEWER_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)};
add(module->And(NEWER_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
add({b[i], RTLIL::SigSpec(0, i)}, false, do_subtract);
}
else
{
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
add(module->And(NEWER_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
a = {a.extract(0, width-1), State::S0};
}
}
@ -108,10 +108,10 @@ struct MaccmapWorker
in3 = in3.extract(start_index, stop_index-start_index);
int width = GetSize(in1);
RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
RTLIL::Wire *w1 = module->addWire(NEWER_ID, width);
RTLIL::Wire *w2 = module->addWire(NEWER_ID, width);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($fa));
cell->setParam(ID::WIDTH, width);
cell->setPort(ID::A, in1);
cell->setPort(ID::B, in2);
@ -237,14 +237,14 @@ struct MaccmapWorker
}
RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu));
RTLIL::Cell *c = module->addCell(NEWER_ID, ID($alu));
c->setPort(ID::A, summands.front());
c->setPort(ID::B, summands.back());
c->setPort(ID::CI, State::S0);
c->setPort(ID::BI, State::S0);
c->setPort(ID::Y, module->addWire(NEW_ID, width));
c->setPort(ID::X, module->addWire(NEW_ID, width));
c->setPort(ID::CO, module->addWire(NEW_ID, width));
c->setPort(ID::Y, module->addWire(NEWER_ID, width));
c->setPort(ID::X, module->addWire(NEWER_ID, width));
c->setPort(ID::CO, module->addWire(NEWER_ID, width));
c->fixup_parameters();
if (!tree_sum_bits.empty()) {
@ -296,16 +296,16 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (auto &term : macc.terms) {
summand_t this_summand;
if (GetSize(term.in_b)) {
this_summand.first = module->addWire(NEW_ID, width);
module->addMul(NEW_ID, term.in_a, term.in_b, this_summand.first, term.is_signed);
this_summand.first = module->addWire(NEWER_ID, width);
module->addMul(NEWER_ID, term.in_a, term.in_b, this_summand.first, term.is_signed);
} else if (GetSize(term.in_a) == 1 && GetSize(term.in_b) == 0 && !term.is_signed && !term.do_subtract) {
// Mimic old 'bit_terms' treatment in case it's relevant for performance,
// i.e. defer single-bit summands to be the last ones
bit_terms.append(term.in_a);
continue;
} else if (GetSize(term.in_a) != width) {
this_summand.first = module->addWire(NEW_ID, width);
module->addPos(NEW_ID, term.in_a, this_summand.first, term.is_signed);
this_summand.first = module->addWire(NEWER_ID, width);
module->addPos(NEWER_ID, term.in_a, this_summand.first, term.is_signed);
} else {
this_summand.first = term.in_a;
}
@ -325,14 +325,14 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (int i = 0; i < GetSize(summands); i += 2) {
if (i+1 < GetSize(summands)) {
summand_t this_summand;
this_summand.first = module->addWire(NEW_ID, width);
this_summand.first = module->addWire(NEWER_ID, width);
this_summand.second = summands[i].second && summands[i+1].second;
if (summands[i].second == summands[i+1].second)
module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
module->addAdd(NEWER_ID, summands[i].first, summands[i+1].first, this_summand.first);
else if (summands[i].second)
module->addSub(NEW_ID, summands[i+1].first, summands[i].first, this_summand.first);
module->addSub(NEWER_ID, summands[i+1].first, summands[i].first, this_summand.first);
else if (summands[i+1].second)
module->addSub(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
module->addSub(NEWER_ID, summands[i].first, summands[i+1].first, this_summand.first);
else
log_abort();
new_summands.push_back(this_summand);
@ -343,7 +343,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
}
if (summands.front().second)
module->addNeg(NEW_ID, summands.front().first, cell->getPort(ID::Y));
module->addNeg(NEWER_ID, summands.front().first, cell->getPort(ID::Y));
else
module->connect(cell->getPort(ID::Y), summands.front().first);
}

16
passes/techmap/muxcover.cc
View file

@ -185,7 +185,7 @@ struct MuxcoverWorker
tuple<SigBit, SigBit, SigBit> key(A, B, sel);
if (decode_mux_cache.count(key) == 0) {
auto &entry = decode_mux_cache[key];
std::get<0>(entry) = module->addWire(NEW_ID);
std::get<0>(entry) = module->addWire(NEWER_ID);
std::get<2>(entry) = false;
decode_mux_reverse_cache[std::get<0>(entry)] = key;
}
@ -215,11 +215,11 @@ struct MuxcoverWorker
implement_decode_mux(std::get<1>(key));
if (std::get<0>(key) == State::Sx) {
module->addBufGate(NEW_ID, std::get<1>(key), ctrl_bit);
module->addBufGate(NEWER_ID, std::get<1>(key), ctrl_bit);
} else if (std::get<1>(key) == State::Sx) {
module->addBufGate(NEW_ID, std::get<0>(key), ctrl_bit);
module->addBufGate(NEWER_ID, std::get<0>(key), ctrl_bit);
} else {
module->addMuxGate(NEW_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit);
module->addMuxGate(NEWER_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit);
decode_mux_counter++;
}
std::get<2>(entry) = true;
@ -513,7 +513,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 2) {
count_muxes_by_type[0]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
Cell *cell = module->addCell(NEWER_ID, ID($_MUX_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::S, mux.selects[0]);
@ -523,7 +523,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 4) {
count_muxes_by_type[1]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
Cell *cell = module->addCell(NEWER_ID, ID($_MUX4_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::C, mux.inputs[2]);
@ -536,7 +536,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 8) {
count_muxes_by_type[2]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
Cell *cell = module->addCell(NEWER_ID, ID($_MUX8_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::C, mux.inputs[2]);
@ -554,7 +554,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 16) {
count_muxes_by_type[3]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
Cell *cell = module->addCell(NEWER_ID, ID($_MUX16_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::C, mux.inputs[2]);

10
passes/techmap/pmuxtree.cc
View file

@ -32,9 +32,9 @@ static SigSpec or_generator(Module *module, const SigSpec &sig)
case 1:
return sig;
case 2:
return module->Or(NEW_ID, sig[0], sig[1]);
return module->Or(NEWER_ID, sig[0], sig[1]);
default:
return module->ReduceOr(NEW_ID, sig);
return module->ReduceOr(NEWER_ID, sig);
}
}
@ -62,7 +62,7 @@ static SigSpec recursive_mux_generator(Module *module, const SigSpec &sig_data,
left_or = or_generator(module, left_or);
sig_or.append(left_or);
return module->Mux(NEW_ID, right_result, left_result, left_or);
return module->Mux(NEWER_ID, right_result, left_result, left_or);
}
struct PmuxtreePass : public Pass {
@ -97,8 +97,8 @@ struct PmuxtreePass : public Pass {
if (!cell->getPort(ID::A).is_fully_undef()) {
sig_data.append(cell->getPort(ID::A));
SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel);
sig_sel.append(module->Not(NEW_ID, sig_sel_or));
SigSpec sig_sel_or = module->ReduceOr(NEWER_ID, sig_sel);
sig_sel.append(module->Not(NEWER_ID, sig_sel_or));
}
SigSpec result, result_or;

4
passes/techmap/shregmap.cc
View file

@ -75,7 +75,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech
auto D = cell->getPort(ID::D);
auto C = cell->getPort(ID::C);
auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG));
auto newcell = cell->module->addCell(NEWER_ID, ID(GP_SHREG));
newcell->setPort(ID(nRST), State::S1);
newcell->setPort(ID::CLK, C);
newcell->setPort(ID(IN), D);
@ -142,7 +142,7 @@ struct ShregmapWorker
// so that it can be identified as another chain
// (omitting this common flop)
// Link: https://github.com/YosysHQ/yosys/pull/1085
Wire *wire = module->addWire(NEW_ID);
Wire *wire = module->addWire(NEWER_ID);
module->connect(wire, d_bit);
sigmap.add(wire, d_bit);
sigbit_chain_next.insert(std::make_pair(wire, cell));

48
passes/techmap/simplemap.cc
View file

@ -35,7 +35,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::Y, sig_y[i]);
@ -80,7 +80,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
log_assert(!gate_type.empty());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type);
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
@ -122,7 +122,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
while (sig_a.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
RTLIL::SigSpec sig_t = module->addWire(NEWER_ID, sig_a.size() / 2);
for (int i = 0; i < sig_a.size(); i += 2)
{
@ -131,7 +131,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type);
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_a[i+1]);
@ -143,8 +143,8 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
}
if (cell->type == ID($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::SigSpec sig_t = module->addWire(NEWER_ID);
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_t);
@ -163,7 +163,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
{
while (sig.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
RTLIL::SigSpec sig_t = module->addWire(NEWER_ID, sig.size() / 2);
for (int i = 0; i < sig.size(); i += 2)
{
@ -172,7 +172,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_OR_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig[i]);
gate->setPort(ID::B, sig[i+1]);
@ -201,7 +201,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
sig_y = sig_y.extract(0, 1);
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_y);
@ -230,7 +230,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type);
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a);
gate->setPort(ID::B, sig_b);
@ -245,20 +245,20 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool is_ne = cell->type.in(ID($ne), ID($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
RTLIL::SigSpec xor_out = module->addWire(NEWER_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEWER_ID, sig_a, sig_b, xor_out, is_signed);
xor_cell->attributes[ID::src] = cell->attributes[ID::src];
simplemap_bitop(module, xor_cell);
module->remove(xor_cell);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEWER_ID);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEWER_ID, xor_out, reduce_out);
reduce_cell->attributes[ID::src] = cell->attributes[ID::src];
simplemap_reduce(module, reduce_cell);
module->remove(reduce_cell);
if (!is_ne) {
RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
RTLIL::Cell *not_cell = module->addLogicNot(NEWER_ID, reduce_out, sig_y);
not_cell->attributes[ID::src] = cell->attributes[ID::src];
simplemap_lognot(module, not_cell);
module->remove(not_cell);
@ -272,7 +272,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
@ -289,7 +289,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
@ -305,7 +305,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_TBUF_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::E, sig_e);
@ -320,10 +320,10 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
int width = GetSize(cell->getPort(ID::Y));
for (int idx = 0; idx < GetSize(sel); idx++) {
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
SigSpec new_data = module->addWire(NEWER_ID, GetSize(data)/2);
for (int i = 0; i < GetSize(new_data); i += width) {
for (int k = 0; k < width; k++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, data[i*2+k]);
gate->setPort(ID::B, data[i*2+width+k]);
@ -344,9 +344,9 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int());
for (int idx = 0; GetSize(lut_data) > 1; idx++) {
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
SigSpec new_lut_data = module->addWire(NEWER_ID, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, lut_data[i]);
gate->setPort(ID::B, lut_data[i+1]);
@ -383,10 +383,10 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1);
products.append(GetSize(in) > 0 ? module->Eq(NEWER_ID, in, pat) : State::S1);
}
module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID, products));
module->connect(cell->getPort(ID::Y), module->ReduceOr(NEWER_ID, products));
}
void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)

4
passes/techmap/techmap.cc
View file

@ -205,7 +205,7 @@ struct TechmapWorker
RTLIL::Wire *w = module->wire(w_name);
if (w != nullptr) {
temp_renamed_wires[w] = w->name;
module->rename(w, NEW_ID);
module->rename(w, NEWER_ID);
w = nullptr;
}
if (w == nullptr) {
@ -792,7 +792,7 @@ struct TechmapWorker
continue;
IdString port_name = wire->name;
tpl->rename(wire, NEW_ID);
tpl->rename(wire, NEWER_ID);
RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
wire->port_input = false;

12
passes/techmap/tribuf.cc
View file

@ -93,7 +93,7 @@ struct TribufWorker {
}
if (is_all_z(cell->getPort(ID::B))) {
cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID::S)));
cell->setPort(en_port, module->Not(NEWER_ID, cell->getPort(ID::S)));
cell->unsetPort(ID::B);
cell->unsetPort(ID::S);
cell->type = tri_type;
@ -138,12 +138,12 @@ struct TribufWorker {
auto cell_s = cell->type == ID($tribuf) ? cell->getPort(ID::EN) : cell->getPort(ID::E);
auto other_s = module->ReduceOr(NEW_ID, others_s);
auto other_s = module->ReduceOr(NEWER_ID, others_s);
auto conflict = module->And(NEW_ID, cell_s, other_s);
auto conflict = module->And(NEWER_ID, cell_s, other_s);
std::string name = stringf("$tribuf_conflict$%s", log_id(cell->name));
auto assert_cell = module->addAssert(name, module->Not(NEW_ID, conflict), SigSpec(true));
auto assert_cell = module->addAssert(name, module->Not(NEWER_ID, conflict), SigSpec(true));
assert_cell->set_src_attribute(cell->get_src_attribute());
assert_cell->set_bool_attribute(ID::keep);
@ -162,12 +162,12 @@ struct TribufWorker {
module->remove(cell);
}
SigSpec muxout = GetSize(pmux_s) > 1 ? module->Pmux(NEW_ID, SigSpec(State::Sx, GetSize(it.first)), pmux_b, pmux_s) : pmux_b;
SigSpec muxout = GetSize(pmux_s) > 1 ? module->Pmux(NEWER_ID, SigSpec(State::Sx, GetSize(it.first)), pmux_b, pmux_s) : pmux_b;
if (no_tribuf)
module->connect(it.first, muxout);
else {
module->addTribuf(NEW_ID, muxout, module->ReduceOr(NEW_ID, pmux_s), it.first);
module->addTribuf(NEWER_ID, muxout, module->ReduceOr(NEWER_ID, pmux_s), it.first);
module->design->scratchpad_set_bool("tribuf.added_something", true);
}
}

6
passes/tests/test_cell.cc
View file

@ -364,9 +364,9 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
}
if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B));
auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y)));
module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y));
auto b_not_zero = module->ReduceBool(NEWER_ID, cell->getPort(ID::B));
auto div_out = module->addWire(NEWER_ID, GetSize(cell->getPort(ID::Y)));
module->addMux(NEWER_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y));
cell->setPort(ID::Y, div_out);
}