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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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104
kernel/ff.cc
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@ -263,7 +263,7 @@ FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initva
}
FfData FfData::slice(const std::vector<int> &bits) {
FfData res(module, initvals, NEW_ID);
FfData res(module, initvals, NEWER_ID);
res.sig_clk = sig_clk;
res.sig_ce = sig_ce;
res.sig_aload = sig_aload;
@ -417,21 +417,21 @@ void FfData::aload_to_sr() {
pol_clr = false;
pol_set = true;
if (pol_aload) {
sig_clr = module->Mux(NEW_ID, Const(State::S1, width), sig_ad, sig_aload);
sig_set = module->Mux(NEW_ID, Const(State::S0, width), sig_ad, sig_aload);
sig_clr = module->Mux(NEWER_ID, Const(State::S1, width), sig_ad, sig_aload);
sig_set = module->Mux(NEWER_ID, Const(State::S0, width), sig_ad, sig_aload);
} else {
sig_clr = module->Mux(NEW_ID, sig_ad, Const(State::S1, width), sig_aload);
sig_set = module->Mux(NEW_ID, sig_ad, Const(State::S0, width), sig_aload);
sig_clr = module->Mux(NEWER_ID, sig_ad, Const(State::S1, width), sig_aload);
sig_set = module->Mux(NEWER_ID, sig_ad, Const(State::S0, width), sig_aload);
}
} else {
pol_clr = pol_aload;
pol_set = pol_aload;
if (pol_aload) {
sig_clr = module->AndnotGate(NEW_ID, sig_aload, sig_ad);
sig_set = module->AndGate(NEW_ID, sig_aload, sig_ad);
sig_clr = module->AndnotGate(NEWER_ID, sig_aload, sig_ad);
sig_set = module->AndGate(NEWER_ID, sig_aload, sig_ad);
} else {
sig_clr = module->OrGate(NEW_ID, sig_aload, sig_ad);
sig_set = module->OrnotGate(NEW_ID, sig_aload, sig_ad);
sig_clr = module->OrGate(NEWER_ID, sig_aload, sig_ad);
sig_set = module->OrnotGate(NEWER_ID, sig_aload, sig_ad);
}
}
}
@ -444,31 +444,31 @@ void FfData::convert_ce_over_srst(bool val) {
if (!is_fine) {
if (pol_ce) {
if (pol_srst) {
sig_ce = module->Or(NEW_ID, sig_ce, sig_srst);
sig_ce = module->Or(NEWER_ID, sig_ce, sig_srst);
} else {
SigSpec tmp = module->Not(NEW_ID, sig_srst);
sig_ce = module->Or(NEW_ID, sig_ce, tmp);
SigSpec tmp = module->Not(NEWER_ID, sig_srst);
sig_ce = module->Or(NEWER_ID, sig_ce, tmp);
}
} else {
if (pol_srst) {
SigSpec tmp = module->Not(NEW_ID, sig_srst);
sig_ce = module->And(NEW_ID, sig_ce, tmp);
SigSpec tmp = module->Not(NEWER_ID, sig_srst);
sig_ce = module->And(NEWER_ID, sig_ce, tmp);
} else {
sig_ce = module->And(NEW_ID, sig_ce, sig_srst);
sig_ce = module->And(NEWER_ID, sig_ce, sig_srst);
}
}
} else {
if (pol_ce) {
if (pol_srst) {
sig_ce = module->OrGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->OrGate(NEWER_ID, sig_ce, sig_srst);
} else {
sig_ce = module->OrnotGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->OrnotGate(NEWER_ID, sig_ce, sig_srst);
}
} else {
if (pol_srst) {
sig_ce = module->AndnotGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->AndnotGate(NEWER_ID, sig_ce, sig_srst);
} else {
sig_ce = module->AndGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->AndGate(NEWER_ID, sig_ce, sig_srst);
}
}
}
@ -477,31 +477,31 @@ void FfData::convert_ce_over_srst(bool val) {
if (!is_fine) {
if (pol_srst) {
if (pol_ce) {
sig_srst = cell->module->And(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->And(NEWER_ID, sig_srst, sig_ce);
} else {
SigSpec tmp = module->Not(NEW_ID, sig_ce);
sig_srst = cell->module->And(NEW_ID, sig_srst, tmp);
SigSpec tmp = module->Not(NEWER_ID, sig_ce);
sig_srst = cell->module->And(NEWER_ID, sig_srst, tmp);
}
} else {
if (pol_ce) {
SigSpec tmp = module->Not(NEW_ID, sig_ce);
sig_srst = cell->module->Or(NEW_ID, sig_srst, tmp);
SigSpec tmp = module->Not(NEWER_ID, sig_ce);
sig_srst = cell->module->Or(NEWER_ID, sig_srst, tmp);
} else {
sig_srst = cell->module->Or(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->Or(NEWER_ID, sig_srst, sig_ce);
}
}
} else {
if (pol_srst) {
if (pol_ce) {
sig_srst = cell->module->AndGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->AndGate(NEWER_ID, sig_srst, sig_ce);
} else {
sig_srst = cell->module->AndnotGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->AndnotGate(NEWER_ID, sig_srst, sig_ce);
}
} else {
if (pol_ce) {
sig_srst = cell->module->OrnotGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->OrnotGate(NEWER_ID, sig_srst, sig_ce);
} else {
sig_srst = cell->module->OrGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->OrGate(NEWER_ID, sig_srst, sig_ce);
}
}
}
@ -518,14 +518,14 @@ void FfData::unmap_ce() {
if (!is_fine) {
if (pol_ce)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, sig_ce);
sig_d = module->Mux(NEWER_ID, sig_q, sig_d, sig_ce);
else
sig_d = module->Mux(NEW_ID, sig_d, sig_q, sig_ce);
sig_d = module->Mux(NEWER_ID, sig_d, sig_q, sig_ce);
} else {
if (pol_ce)
sig_d = module->MuxGate(NEW_ID, sig_q, sig_d, sig_ce);
sig_d = module->MuxGate(NEWER_ID, sig_q, sig_d, sig_ce);
else
sig_d = module->MuxGate(NEW_ID, sig_d, sig_q, sig_ce);
sig_d = module->MuxGate(NEWER_ID, sig_d, sig_q, sig_ce);
}
has_ce = false;
}
@ -538,14 +538,14 @@ void FfData::unmap_srst() {
if (!is_fine) {
if (pol_srst)
sig_d = module->Mux(NEW_ID, sig_d, val_srst, sig_srst);
sig_d = module->Mux(NEWER_ID, sig_d, val_srst, sig_srst);
else
sig_d = module->Mux(NEW_ID, val_srst, sig_d, sig_srst);
sig_d = module->Mux(NEWER_ID, val_srst, sig_d, sig_srst);
} else {
if (pol_srst)
sig_d = module->MuxGate(NEW_ID, sig_d, val_srst[0], sig_srst);
sig_d = module->MuxGate(NEWER_ID, sig_d, val_srst[0], sig_srst);
else
sig_d = module->MuxGate(NEW_ID, val_srst[0], sig_d, sig_srst);
sig_d = module->MuxGate(NEWER_ID, val_srst[0], sig_d, sig_srst);
}
has_srst = false;
}
@ -718,7 +718,7 @@ void FfData::flip_bits(const pool<int> &bits) {
flip_rst_bits(bits);
Wire *new_q = module->addWire(NEW_ID, width);
Wire *new_q = module->addWire(NEWER_ID, width);
if (has_sr && cell) {
log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", log_id(module->name), log_id(cell->name), log_id(cell->type));
@ -730,15 +730,15 @@ void FfData::flip_bits(const pool<int> &bits) {
SigSpec new_sig_clr;
if (pol_set) {
if (pol_clr) {
new_sig_clr = module->AndnotGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->AndnotGate(NEWER_ID, sig_set, sig_clr);
} else {
new_sig_clr = module->AndGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->AndGate(NEWER_ID, sig_set, sig_clr);
}
} else {
if (pol_clr) {
new_sig_clr = module->OrGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->OrGate(NEWER_ID, sig_set, sig_clr);
} else {
new_sig_clr = module->OrnotGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->OrnotGate(NEWER_ID, sig_set, sig_clr);
}
}
pol_set = pol_clr;
@ -747,10 +747,10 @@ void FfData::flip_bits(const pool<int> &bits) {
sig_clr = new_sig_clr;
}
if (has_clk || has_gclk)
sig_d = module->NotGate(NEW_ID, sig_d);
sig_d = module->NotGate(NEWER_ID, sig_d);
if (has_aload)
sig_ad = module->NotGate(NEW_ID, sig_ad);
module->addNotGate(NEW_ID, new_q, sig_q);
sig_ad = module->NotGate(NEWER_ID, sig_ad);
module->addNotGate(NEWER_ID, new_q, sig_q);
}
else
{
@ -758,17 +758,17 @@ void FfData::flip_bits(const pool<int> &bits) {
SigSpec not_clr;
if (!pol_clr) {
not_clr = sig_clr;
sig_clr = module->Not(NEW_ID, sig_clr);
sig_clr = module->Not(NEWER_ID, sig_clr);
pol_clr = true;
} else {
not_clr = module->Not(NEW_ID, sig_clr);
not_clr = module->Not(NEWER_ID, sig_clr);
}
if (!pol_set) {
sig_set = module->Not(NEW_ID, sig_set);
sig_set = module->Not(NEWER_ID, sig_set);
pol_set = true;
}
SigSpec masked_set = module->And(NEW_ID, sig_set, not_clr);
SigSpec masked_set = module->And(NEWER_ID, sig_set, not_clr);
for (auto bit: bits) {
sig_set[bit] = sig_clr[bit];
sig_clr[bit] = masked_set[bit];
@ -780,10 +780,10 @@ void FfData::flip_bits(const pool<int> &bits) {
mask.set(bit, State::S1);
if (has_clk || has_gclk)
sig_d = module->Xor(NEW_ID, sig_d, mask);
sig_d = module->Xor(NEWER_ID, sig_d, mask);
if (has_aload)
sig_ad = module->Xor(NEW_ID, sig_ad, mask);
module->addXor(NEW_ID, new_q, mask, sig_q);
sig_ad = module->Xor(NEWER_ID, sig_ad, mask);
module->addXor(NEWER_ID, new_q, mask, sig_q);
}
sig_q = new_q;