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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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104
kernel/ff.cc
View file

@ -263,7 +263,7 @@ FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initva
}
FfData FfData::slice(const std::vector<int> &bits) {
FfData res(module, initvals, NEW_ID);
FfData res(module, initvals, NEWER_ID);
res.sig_clk = sig_clk;
res.sig_ce = sig_ce;
res.sig_aload = sig_aload;
@ -417,21 +417,21 @@ void FfData::aload_to_sr() {
pol_clr = false;
pol_set = true;
if (pol_aload) {
sig_clr = module->Mux(NEW_ID, Const(State::S1, width), sig_ad, sig_aload);
sig_set = module->Mux(NEW_ID, Const(State::S0, width), sig_ad, sig_aload);
sig_clr = module->Mux(NEWER_ID, Const(State::S1, width), sig_ad, sig_aload);
sig_set = module->Mux(NEWER_ID, Const(State::S0, width), sig_ad, sig_aload);
} else {
sig_clr = module->Mux(NEW_ID, sig_ad, Const(State::S1, width), sig_aload);
sig_set = module->Mux(NEW_ID, sig_ad, Const(State::S0, width), sig_aload);
sig_clr = module->Mux(NEWER_ID, sig_ad, Const(State::S1, width), sig_aload);
sig_set = module->Mux(NEWER_ID, sig_ad, Const(State::S0, width), sig_aload);
}
} else {
pol_clr = pol_aload;
pol_set = pol_aload;
if (pol_aload) {
sig_clr = module->AndnotGate(NEW_ID, sig_aload, sig_ad);
sig_set = module->AndGate(NEW_ID, sig_aload, sig_ad);
sig_clr = module->AndnotGate(NEWER_ID, sig_aload, sig_ad);
sig_set = module->AndGate(NEWER_ID, sig_aload, sig_ad);
} else {
sig_clr = module->OrGate(NEW_ID, sig_aload, sig_ad);
sig_set = module->OrnotGate(NEW_ID, sig_aload, sig_ad);
sig_clr = module->OrGate(NEWER_ID, sig_aload, sig_ad);
sig_set = module->OrnotGate(NEWER_ID, sig_aload, sig_ad);
}
}
}
@ -444,31 +444,31 @@ void FfData::convert_ce_over_srst(bool val) {
if (!is_fine) {
if (pol_ce) {
if (pol_srst) {
sig_ce = module->Or(NEW_ID, sig_ce, sig_srst);
sig_ce = module->Or(NEWER_ID, sig_ce, sig_srst);
} else {
SigSpec tmp = module->Not(NEW_ID, sig_srst);
sig_ce = module->Or(NEW_ID, sig_ce, tmp);
SigSpec tmp = module->Not(NEWER_ID, sig_srst);
sig_ce = module->Or(NEWER_ID, sig_ce, tmp);
}
} else {
if (pol_srst) {
SigSpec tmp = module->Not(NEW_ID, sig_srst);
sig_ce = module->And(NEW_ID, sig_ce, tmp);
SigSpec tmp = module->Not(NEWER_ID, sig_srst);
sig_ce = module->And(NEWER_ID, sig_ce, tmp);
} else {
sig_ce = module->And(NEW_ID, sig_ce, sig_srst);
sig_ce = module->And(NEWER_ID, sig_ce, sig_srst);
}
}
} else {
if (pol_ce) {
if (pol_srst) {
sig_ce = module->OrGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->OrGate(NEWER_ID, sig_ce, sig_srst);
} else {
sig_ce = module->OrnotGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->OrnotGate(NEWER_ID, sig_ce, sig_srst);
}
} else {
if (pol_srst) {
sig_ce = module->AndnotGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->AndnotGate(NEWER_ID, sig_ce, sig_srst);
} else {
sig_ce = module->AndGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->AndGate(NEWER_ID, sig_ce, sig_srst);
}
}
}
@ -477,31 +477,31 @@ void FfData::convert_ce_over_srst(bool val) {
if (!is_fine) {
if (pol_srst) {
if (pol_ce) {
sig_srst = cell->module->And(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->And(NEWER_ID, sig_srst, sig_ce);
} else {
SigSpec tmp = module->Not(NEW_ID, sig_ce);
sig_srst = cell->module->And(NEW_ID, sig_srst, tmp);
SigSpec tmp = module->Not(NEWER_ID, sig_ce);
sig_srst = cell->module->And(NEWER_ID, sig_srst, tmp);
}
} else {
if (pol_ce) {
SigSpec tmp = module->Not(NEW_ID, sig_ce);
sig_srst = cell->module->Or(NEW_ID, sig_srst, tmp);
SigSpec tmp = module->Not(NEWER_ID, sig_ce);
sig_srst = cell->module->Or(NEWER_ID, sig_srst, tmp);
} else {
sig_srst = cell->module->Or(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->Or(NEWER_ID, sig_srst, sig_ce);
}
}
} else {
if (pol_srst) {
if (pol_ce) {
sig_srst = cell->module->AndGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->AndGate(NEWER_ID, sig_srst, sig_ce);
} else {
sig_srst = cell->module->AndnotGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->AndnotGate(NEWER_ID, sig_srst, sig_ce);
}
} else {
if (pol_ce) {
sig_srst = cell->module->OrnotGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->OrnotGate(NEWER_ID, sig_srst, sig_ce);
} else {
sig_srst = cell->module->OrGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->OrGate(NEWER_ID, sig_srst, sig_ce);
}
}
}
@ -518,14 +518,14 @@ void FfData::unmap_ce() {
if (!is_fine) {
if (pol_ce)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, sig_ce);
sig_d = module->Mux(NEWER_ID, sig_q, sig_d, sig_ce);
else
sig_d = module->Mux(NEW_ID, sig_d, sig_q, sig_ce);
sig_d = module->Mux(NEWER_ID, sig_d, sig_q, sig_ce);
} else {
if (pol_ce)
sig_d = module->MuxGate(NEW_ID, sig_q, sig_d, sig_ce);
sig_d = module->MuxGate(NEWER_ID, sig_q, sig_d, sig_ce);
else
sig_d = module->MuxGate(NEW_ID, sig_d, sig_q, sig_ce);
sig_d = module->MuxGate(NEWER_ID, sig_d, sig_q, sig_ce);
}
has_ce = false;
}
@ -538,14 +538,14 @@ void FfData::unmap_srst() {
if (!is_fine) {
if (pol_srst)
sig_d = module->Mux(NEW_ID, sig_d, val_srst, sig_srst);
sig_d = module->Mux(NEWER_ID, sig_d, val_srst, sig_srst);
else
sig_d = module->Mux(NEW_ID, val_srst, sig_d, sig_srst);
sig_d = module->Mux(NEWER_ID, val_srst, sig_d, sig_srst);
} else {
if (pol_srst)
sig_d = module->MuxGate(NEW_ID, sig_d, val_srst[0], sig_srst);
sig_d = module->MuxGate(NEWER_ID, sig_d, val_srst[0], sig_srst);
else
sig_d = module->MuxGate(NEW_ID, val_srst[0], sig_d, sig_srst);
sig_d = module->MuxGate(NEWER_ID, val_srst[0], sig_d, sig_srst);
}
has_srst = false;
}
@ -718,7 +718,7 @@ void FfData::flip_bits(const pool<int> &bits) {
flip_rst_bits(bits);
Wire *new_q = module->addWire(NEW_ID, width);
Wire *new_q = module->addWire(NEWER_ID, width);
if (has_sr && cell) {
log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", log_id(module->name), log_id(cell->name), log_id(cell->type));
@ -730,15 +730,15 @@ void FfData::flip_bits(const pool<int> &bits) {
SigSpec new_sig_clr;
if (pol_set) {
if (pol_clr) {
new_sig_clr = module->AndnotGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->AndnotGate(NEWER_ID, sig_set, sig_clr);
} else {
new_sig_clr = module->AndGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->AndGate(NEWER_ID, sig_set, sig_clr);
}
} else {
if (pol_clr) {
new_sig_clr = module->OrGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->OrGate(NEWER_ID, sig_set, sig_clr);
} else {
new_sig_clr = module->OrnotGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->OrnotGate(NEWER_ID, sig_set, sig_clr);
}
}
pol_set = pol_clr;
@ -747,10 +747,10 @@ void FfData::flip_bits(const pool<int> &bits) {
sig_clr = new_sig_clr;
}
if (has_clk || has_gclk)
sig_d = module->NotGate(NEW_ID, sig_d);
sig_d = module->NotGate(NEWER_ID, sig_d);
if (has_aload)
sig_ad = module->NotGate(NEW_ID, sig_ad);
module->addNotGate(NEW_ID, new_q, sig_q);
sig_ad = module->NotGate(NEWER_ID, sig_ad);
module->addNotGate(NEWER_ID, new_q, sig_q);
}
else
{
@ -758,17 +758,17 @@ void FfData::flip_bits(const pool<int> &bits) {
SigSpec not_clr;
if (!pol_clr) {
not_clr = sig_clr;
sig_clr = module->Not(NEW_ID, sig_clr);
sig_clr = module->Not(NEWER_ID, sig_clr);
pol_clr = true;
} else {
not_clr = module->Not(NEW_ID, sig_clr);
not_clr = module->Not(NEWER_ID, sig_clr);
}
if (!pol_set) {
sig_set = module->Not(NEW_ID, sig_set);
sig_set = module->Not(NEWER_ID, sig_set);
pol_set = true;
}
SigSpec masked_set = module->And(NEW_ID, sig_set, not_clr);
SigSpec masked_set = module->And(NEWER_ID, sig_set, not_clr);
for (auto bit: bits) {
sig_set[bit] = sig_clr[bit];
sig_clr[bit] = masked_set[bit];
@ -780,10 +780,10 @@ void FfData::flip_bits(const pool<int> &bits) {
mask.set(bit, State::S1);
if (has_clk || has_gclk)
sig_d = module->Xor(NEW_ID, sig_d, mask);
sig_d = module->Xor(NEWER_ID, sig_d, mask);
if (has_aload)
sig_ad = module->Xor(NEW_ID, sig_ad, mask);
module->addXor(NEW_ID, new_q, mask, sig_q);
sig_ad = module->Xor(NEWER_ID, sig_ad, mask);
module->addXor(NEWER_ID, new_q, mask, sig_q);
}
sig_q = new_q;

4
kernel/ffmerge.cc
View file

@ -29,7 +29,7 @@ bool FfMergeHelper::is_output_unused(RTLIL::SigSpec sig) {
}
bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits) {
ff = FfData(module, initvals, NEW_ID);
ff = FfData(module, initvals, NEWER_ID);
sigmap->apply(sig);
bool found = false;
@ -157,7 +157,7 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pai
}
bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits) {
ff = FfData(module, initvals, NEW_ID);
ff = FfData(module, initvals, NEWER_ID);
sigmap->apply(sig);
bool found = false;

90
kernel/mem.cc
View file

@ -122,7 +122,7 @@ void Mem::emit() {
}
if (!cell) {
if (memid.empty())
memid = NEW_ID;
memid = NEWER_ID;
cell = module->addCell(memid, ID($mem_v2));
}
cell->type = ID($mem_v2);
@ -291,7 +291,7 @@ void Mem::emit() {
}
if (!mem) {
if (memid.empty())
memid = NEW_ID;
memid = NEWER_ID;
mem = new RTLIL::Memory;
mem->name = memid;
module->memories[memid] = mem;
@ -302,7 +302,7 @@ void Mem::emit() {
mem->attributes = attributes;
for (auto &port : rd_ports) {
if (!port.cell)
port.cell = module->addCell(NEW_ID, ID($memrd_v2));
port.cell = module->addCell(NEWER_ID, ID($memrd_v2));
port.cell->type = ID($memrd_v2);
port.cell->attributes = port.attributes;
port.cell->parameters[ID::MEMID] = memid.str();
@ -327,7 +327,7 @@ void Mem::emit() {
int idx = 0;
for (auto &port : wr_ports) {
if (!port.cell)
port.cell = module->addCell(NEW_ID, ID($memwr_v2));
port.cell = module->addCell(NEWER_ID, ID($memwr_v2));
port.cell->type = ID($memwr_v2);
port.cell->attributes = port.attributes;
if (port.cell->parameters.count(ID::PRIORITY))
@ -348,7 +348,7 @@ void Mem::emit() {
for (auto &init : inits) {
bool v2 = !init.en.is_fully_ones();
if (!init.cell)
init.cell = module->addCell(NEW_ID, v2 ? ID($meminit_v2) : ID($meminit));
init.cell = module->addCell(NEWER_ID, v2 ? ID($meminit_v2) : ID($meminit));
else
init.cell->type = v2 ? ID($meminit_v2) : ID($meminit);
init.cell->attributes = init.attributes;
@ -1127,7 +1127,7 @@ void Mem::emulate_priority(int idx1, int idx2, FfInitVals *initvals)
addr1 = port1.sub_addr(sub);
else
addr2 = port2.sub_addr(sub);
SigSpec addr_eq = module->Eq(NEW_ID, addr1, addr2);
SigSpec addr_eq = module->Eq(NEWER_ID, addr1, addr2);
int ewidth = width << min_wide_log2;
int sub1 = wide1 ? sub : 0;
int sub2 = wide1 ? 0 : sub;
@ -1139,9 +1139,9 @@ void Mem::emulate_priority(int idx1, int idx2, FfInitVals *initvals)
if (cache.count(key)) {
en1 = cache[key];
} else {
SigBit active2 = module->And(NEW_ID, addr_eq, en2);
SigBit nactive2 = module->Not(NEW_ID, active2);
en1 = cache[key] = module->And(NEW_ID, en1, nactive2);
SigBit active2 = module->And(NEWER_ID, addr_eq, en2);
SigBit nactive2 = module->Not(NEWER_ID, active2);
en1 = cache[key] = module->And(NEWER_ID, en1, nactive2);
}
}
}
@ -1165,8 +1165,8 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) {
// The write data FF doesn't need full reset/init behavior, as it'll be masked by
// the mux whenever this would be relevant. It does, however, need to have the same
// clock enable signal as the read port.
SigSpec wdata_q = module->addWire(NEW_ID, GetSize(wport.data));
module->addDffe(NEW_ID, rport.clk, rport.en, wport.data, wdata_q, rport.clk_polarity, true);
SigSpec wdata_q = module->addWire(NEWER_ID, GetSize(wport.data));
module->addDffe(NEWER_ID, rport.clk, rport.en, wport.data, wdata_q, rport.clk_polarity, true);
for (int sub = 0; sub < (1 << max_wide_log2); sub += (1 << min_wide_log2)) {
SigSpec raddr = rport.addr;
SigSpec waddr = wport.addr;
@ -1177,26 +1177,26 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) {
raddr = rport.sub_addr(sub);
SigSpec addr_eq;
if (raddr != waddr)
addr_eq = module->Eq(NEW_ID, raddr, waddr);
addr_eq = module->Eq(NEWER_ID, raddr, waddr);
int pos = 0;
int ewidth = width << min_wide_log2;
int wsub = wide_write ? sub : 0;
int rsub = wide_write ? 0 : sub;
SigSpec rdata_a = module->addWire(NEW_ID, ewidth);
SigSpec rdata_a = module->addWire(NEWER_ID, ewidth);
while (pos < ewidth) {
int epos = pos;
while (epos < ewidth && wport.en[epos + wsub * width] == wport.en[pos + wsub * width])
epos++;
SigSpec cond;
if (raddr != waddr)
cond = module->And(NEW_ID, wport.en[pos + wsub * width], addr_eq);
cond = module->And(NEWER_ID, wport.en[pos + wsub * width], addr_eq);
else
cond = wport.en[pos + wsub * width];
SigSpec cond_q = module->addWire(NEW_ID);
SigSpec cond_q = module->addWire(NEWER_ID);
// The FF for storing the bypass enable signal must be carefully
// constructed to preserve the overall init/reset/enable behavior
// of the whole port.
FfData ff(module, initvals, NEW_ID);
FfData ff(module, initvals, NEWER_ID);
ff.width = 1;
ff.sig_q = cond_q;
ff.sig_d = cond;
@ -1230,7 +1230,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) {
SigSpec cur = rdata_a.extract(pos, epos-pos);
SigSpec other = wdata_q.extract(pos + wsub * width, epos-pos);
SigSpec dest = rport.data.extract(pos + rsub * width, epos-pos);
module->addMux(NEW_ID, cur, other, cond_q, dest);
module->addMux(NEWER_ID, cur, other, cond_q, dest);
pos = epos;
}
rport.data.replace(rsub * width, rdata_a);
@ -1376,8 +1376,8 @@ void Mem::widen_wr_port(int idx, int wide_log2) {
} else {
// May or may not write to this subword.
new_data.append(port.data);
SigSpec addr_eq = module->Eq(NEW_ID, addr_lo, cur_addr_lo);
SigSpec en = module->Mux(NEW_ID, Const(State::S0, GetSize(port.data)), port.en, addr_eq);
SigSpec addr_eq = module->Eq(NEWER_ID, addr_lo, cur_addr_lo);
SigSpec en = module->Mux(NEWER_ID, Const(State::S0, GetSize(port.data)), port.en, addr_eq);
new_en.append(en);
}
}
@ -1392,11 +1392,11 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) {
auto &port = rd_ports[idx];
log_assert(port.clk_enable);
emulate_rd_ce_over_srst(idx);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *prev_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *sel = module->addWire(NEW_ID);
FfData ff_sel(module, initvals, NEW_ID);
FfData ff_data(module, initvals, NEW_ID);
Wire *new_data = module->addWire(NEWER_ID, GetSize(port.data));
Wire *prev_data = module->addWire(NEWER_ID, GetSize(port.data));
Wire *sel = module->addWire(NEWER_ID);
FfData ff_sel(module, initvals, NEWER_ID);
FfData ff_data(module, initvals, NEWER_ID);
ff_sel.width = 1;
ff_sel.has_clk = true;
ff_sel.sig_clk = port.clk;
@ -1444,7 +1444,7 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) {
}
ff_sel.emit();
ff_data.emit();
module->addMux(NEW_ID, prev_data, new_data, sel, port.data);
module->addMux(NEWER_ID, prev_data, new_data, sel, port.data);
port.data = new_data;
port.en = State::S1;
}
@ -1452,9 +1452,9 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) {
void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals) {
auto &port = rd_ports[idx];
if (emu_init && !port.init_value.is_fully_undef()) {
Wire *sel = module->addWire(NEW_ID);
FfData ff_sel(module, initvals, NEW_ID);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *sel = module->addWire(NEWER_ID);
FfData ff_sel(module, initvals, NEWER_ID);
Wire *new_data = module->addWire(NEWER_ID, GetSize(port.data));
ff_sel.width = 1;
ff_sel.has_clk = true;
ff_sel.sig_clk = port.clk;
@ -1493,14 +1493,14 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff
}
}
ff_sel.emit();
module->addMux(NEW_ID, port.init_value, new_data, sel, port.data);
module->addMux(NEWER_ID, port.init_value, new_data, sel, port.data);
port.data = new_data;
port.init_value = Const(State::Sx, GetSize(port.data));
}
if (emu_arst && port.arst != State::S0) {
Wire *sel = module->addWire(NEW_ID);
FfData ff_sel(module, initvals, NEW_ID);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *sel = module->addWire(NEWER_ID);
FfData ff_sel(module, initvals, NEWER_ID);
Wire *new_data = module->addWire(NEWER_ID, GetSize(port.data));
ff_sel.width = 1;
ff_sel.has_clk = true;
ff_sel.sig_clk = port.clk;
@ -1533,14 +1533,14 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff
}
}
ff_sel.emit();
module->addMux(NEW_ID, port.arst_value, new_data, sel, port.data);
module->addMux(NEWER_ID, port.arst_value, new_data, sel, port.data);
port.data = new_data;
port.arst = State::S0;
}
if (emu_srst && port.srst != State::S0) {
Wire *sel = module->addWire(NEW_ID);
FfData ff_sel(module, initvals, NEW_ID);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *sel = module->addWire(NEWER_ID);
FfData ff_sel(module, initvals, NEWER_ID);
Wire *new_data = module->addWire(NEWER_ID, GetSize(port.data));
ff_sel.width = 1;
ff_sel.has_clk = true;
ff_sel.sig_clk = port.clk;
@ -1568,7 +1568,7 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff
ff_sel.val_arst = State::S1;
}
ff_sel.emit();
module->addMux(NEW_ID, port.srst_value, new_data, sel, port.data);
module->addMux(NEWER_ID, port.srst_value, new_data, sel, port.data);
port.data = new_data;
port.srst = State::S0;
}
@ -1582,7 +1582,7 @@ void Mem::emulate_rd_ce_over_srst(int idx) {
return;
}
port.ce_over_srst = false;
port.srst = module->And(NEW_ID, port.en, port.srst);
port.srst = module->And(NEWER_ID, port.en, port.srst);
}
void Mem::emulate_rd_srst_over_ce(int idx) {
@ -1593,7 +1593,7 @@ void Mem::emulate_rd_srst_over_ce(int idx) {
return;
}
port.ce_over_srst = true;
port.en = module->Or(NEW_ID, port.en, port.srst);
port.en = module->Or(NEWER_ID, port.en, port.srst);
}
bool Mem::emulate_read_first_ok() {
@ -1639,13 +1639,13 @@ void Mem::emulate_read_first(FfInitVals *initvals) {
rd_ports[i].transparency_mask[j] = true;
}
for (auto &port: wr_ports) {
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *new_addr = module->addWire(NEW_ID, GetSize(port.addr));
Wire *new_data = module->addWire(NEWER_ID, GetSize(port.data));
Wire *new_addr = module->addWire(NEWER_ID, GetSize(port.addr));
auto compressed = port.compress_en();
Wire *new_en = module->addWire(NEW_ID, GetSize(compressed.first));
FfData ff_data(module, initvals, NEW_ID);
FfData ff_addr(module, initvals, NEW_ID);
FfData ff_en(module, initvals, NEW_ID);
Wire *new_en = module->addWire(NEWER_ID, GetSize(compressed.first));
FfData ff_data(module, initvals, NEWER_ID);
FfData ff_addr(module, initvals, NEWER_ID);
FfData ff_en(module, initvals, NEWER_ID);
ff_data.width = GetSize(port.data);
ff_data.has_clk = true;
ff_data.sig_clk = port.clk;

46
kernel/rtlil.cc
View file

@ -3090,7 +3090,7 @@ RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Pro
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
RTLIL::SigSpec sig_y = addWire(NEWER_ID, _y_size); \
add ## _func(name, sig_a, sig_y, is_signed, src); \
return sig_y; \
}
@ -3115,7 +3115,7 @@ DEF_METHOD(LogicNot, 1, ID($logic_not))
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
RTLIL::SigSpec sig_y = addWire(NEWER_ID, _y_size); \
add ## _func(name, sig_a, sig_y, is_signed, src); \
return sig_y; \
}
@ -3137,7 +3137,7 @@ DEF_METHOD(Buf, sig_a.size(), ID($buf))
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
RTLIL::SigSpec sig_y = addWire(NEWER_ID, _y_size); \
add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
return sig_y; \
}
@ -3180,7 +3180,7 @@ DEF_METHOD(LogicOr, 1, ID($logic_or))
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
RTLIL::SigSpec sig_y = addWire(NEWER_ID, _y_size); \
add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
return sig_y; \
}
@ -3205,7 +3205,7 @@ DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
RTLIL::SigSpec sig_y = addWire(NEWER_ID, _y_size); \
add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
return sig_y; \
}
@ -3225,7 +3225,7 @@ DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
RTLIL::SigSpec sig_y = addWire(NEWER_ID, sig_a.size()); \
add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
return sig_y; \
}
@ -3246,7 +3246,7 @@ DEF_METHOD(Pmux, ID($pmux), 1)
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, _demux ? sig_a.size() << sig_s.size() : sig_a.size() >> sig_s.size()); \
RTLIL::SigSpec sig_y = addWire(NEWER_ID, _demux ? sig_a.size() << sig_s.size() : sig_a.size() >> sig_s.size()); \
add ## _func(name, sig_a, sig_s, sig_y, src); \
return sig_y; \
}
@ -3265,7 +3265,7 @@ DEF_METHOD(Demux, ID($demux), 1)
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
RTLIL::SigSpec sig_y = addWire(NEWER_ID, sig_a.size()); \
add ## _func(name, sig_a, sig_s, sig_y, src); \
return sig_y; \
}
@ -3281,7 +3281,7 @@ DEF_METHOD(Bweqx, ID($bweqx))
return cell; \
} \
RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
RTLIL::SigBit sig2 = addWire(NEW_ID); \
RTLIL::SigBit sig2 = addWire(NEWER_ID); \
add ## _func(name, sig1, sig2, src); \
return sig2; \
}
@ -3295,7 +3295,7 @@ DEF_METHOD(Bweqx, ID($bweqx))
return cell; \
} \
RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
RTLIL::SigBit sig3 = addWire(NEW_ID); \
RTLIL::SigBit sig3 = addWire(NEWER_ID); \
add ## _func(name, sig1, sig2, sig3, src); \
return sig3; \
}
@ -3310,7 +3310,7 @@ DEF_METHOD(Bweqx, ID($bweqx))
return cell; \
} \
RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
RTLIL::SigBit sig4 = addWire(NEW_ID); \
RTLIL::SigBit sig4 = addWire(NEWER_ID); \
add ## _func(name, sig1, sig2, sig3, sig4, src); \
return sig4; \
}
@ -3326,7 +3326,7 @@ DEF_METHOD(Bweqx, ID($bweqx))
return cell; \
} \
RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
RTLIL::SigBit sig5 = addWire(NEW_ID); \
RTLIL::SigBit sig5 = addWire(NEWER_ID); \
add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
return sig5; \
}
@ -3935,7 +3935,7 @@ RTLIL::Cell* RTLIL::Module::addAnyinit(RTLIL::IdString name, const RTLIL::SigSpe
RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
RTLIL::SigSpec sig = addWire(NEWER_ID, width);
Cell *cell = addCell(name, ID($anyconst));
cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
@ -3945,7 +3945,7 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const st
RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
RTLIL::SigSpec sig = addWire(NEWER_ID, width);
Cell *cell = addCell(name, ID($anyseq));
cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
@ -3955,7 +3955,7 @@ RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std:
RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
RTLIL::SigSpec sig = addWire(NEWER_ID, width);
Cell *cell = addCell(name, ID($allconst));
cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
@ -3965,7 +3965,7 @@ RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const st
RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
RTLIL::SigSpec sig = addWire(NEWER_ID, width);
Cell *cell = addCell(name, ID($allseq));
cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
@ -3975,7 +3975,7 @@ RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std:
RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID);
RTLIL::SigSpec sig = addWire(NEWER_ID);
Cell *cell = addCell(name, ID($initstate));
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
@ -3984,7 +3984,7 @@ RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string
RTLIL::SigSpec RTLIL::Module::SetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
RTLIL::SigSpec sig = addWire(NEWER_ID, sig_a.size());
Cell *cell = addCell(name, ID($set_tag));
cell->parameters[ID::WIDTH] = sig_a.size();
cell->parameters[ID::TAG] = tag;
@ -4011,7 +4011,7 @@ RTLIL::Cell* RTLIL::Module::addSetTag(RTLIL::IdString name, const std::string &t
RTLIL::SigSpec RTLIL::Module::GetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
RTLIL::SigSpec sig = addWire(NEWER_ID, sig_a.size());
Cell *cell = addCell(name, ID($get_tag));
cell->parameters[ID::WIDTH] = sig_a.size();
cell->parameters[ID::TAG] = tag;
@ -4035,7 +4035,7 @@ RTLIL::Cell* RTLIL::Module::addOverwriteTag(RTLIL::IdString name, const std::str
RTLIL::SigSpec RTLIL::Module::OriginalTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
RTLIL::SigSpec sig = addWire(NEWER_ID, sig_a.size());
Cell *cell = addCell(name, ID($original_tag));
cell->parameters[ID::WIDTH] = sig_a.size();
cell->parameters[ID::TAG] = tag;
@ -4047,7 +4047,7 @@ RTLIL::SigSpec RTLIL::Module::OriginalTag(RTLIL::IdString name, const std::strin
RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size());
RTLIL::SigSpec sig = addWire(NEWER_ID, sig_e.size());
Cell *cell = addCell(name, ID($future_ff));
cell->parameters[ID::WIDTH] = sig_e.size();
cell->setPort(ID::A, sig_e);
@ -4255,7 +4255,7 @@ void RTLIL::Module::bufNormalize()
for (auto &chunk : sig.chunks())
if (chunk.wire) outWires.insert(chunk.wire);
Wire *wire = addWire(NEW_ID, GetSize(sig));
Wire *wire = addWire(NEWER_ID, GetSize(sig));
sigmap.add(sig, wire);
cell->setPort(portname, wire);
@ -4268,7 +4268,7 @@ void RTLIL::Module::bufNormalize()
for (int i = 0; i < GetSize(wire); i++)
if (insig[i] == outsig[i])
insig[i] = State::Sx;
addBuf(NEW_ID, insig, outsig);
addBuf(NEWER_ID, insig, outsig);
}
}
}