mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-10 17:58:07 +00:00
Code Activity

s/NEW_ID/NEWER_ID/g

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
Download patch file Download diff file Expand all files Collapse all files

10
frontends/aiger/aigerparse.cc
View file

@ -559,9 +559,9 @@ void AigerReader::parse_aiger_ascii()
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
if (clk_wire)
module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
module->addDffGate(NEWER_ID, clk_wire, d_wire, q_wire);
else
module->addFfGate(NEW_ID, d_wire, q_wire);
module->addFfGate(NEWER_ID, d_wire, q_wire);
// Reset logic is optional in AIGER 1.9
if (f.peek() == ' ') {
@ -683,9 +683,9 @@ void AigerReader::parse_aiger_binary()
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
if (clk_wire)
module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
module->addDff(NEWER_ID, clk_wire, d_wire, q_wire);
else
module->addFf(NEW_ID, d_wire, q_wire);
module->addFf(NEWER_ID, d_wire, q_wire);
// Reset logic is optional in AIGER 1.9
if (f.peek() == ' ') {
@ -795,7 +795,7 @@ void AigerReader::post_process()
log_assert(q->port_input);
q->port_input = false;
Cell* ff = module->addFfGate(NEW_ID, d, q);
Cell* ff = module->addFfGate(NEWER_ID, d, q);
ff->attributes[ID::abc9_mergeability] = mergeability[i];
q->attributes[ID::init] = initial_state[i];
}

10
frontends/ast/genrtlil.cc
View file

@ -822,7 +822,7 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::SigSpec check = ast->children[0]->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap());
if (GetSize(check) != 1)
check = current_module->ReduceBool(NEW_ID, check);
check = current_module->ReduceBool(NEWER_ID, check);
Wire *en = current_module->addWire(cellname.str() + "_EN", 1);
set_src_attr(en, ast);
@ -1626,11 +1626,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(fake_ast_width, fake_ast_sign);
if (source_offset != 0) {
shift_val = current_module->Sub(NEW_ID, shift_val, source_offset, fake_ast_sign);
shift_val = current_module->Sub(NEWER_ID, shift_val, source_offset, fake_ast_sign);
fake_ast->children[1]->is_signed = true;
}
if (id2ast->range_swapped) {
shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign);
shift_val = current_module->Sub(NEWER_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign);
fake_ast->children[1]->is_signed = true;
}
if (GetSize(shift_val) >= 32)
@ -2028,7 +2028,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec check = children[0]->genRTLIL();
if (GetSize(check) != 1)
check = current_module->ReduceBool(NEW_ID, check);
check = current_module->ReduceBool(NEWER_ID, check);
RTLIL::Cell *cell = current_module->addCell(cellname, ID($check));
set_src_attr(cell, this);
@ -2130,7 +2130,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} else if (arg->is_signed) {
// non-trivial signed nodes are indirected through
// signed wires to enable sign extension
RTLIL::IdString wire_name = NEW_ID;
RTLIL::IdString wire_name = NEWER_ID;
RTLIL::Wire *wire = current_module->addWire(wire_name, GetSize(sig));
wire->is_signed = true;
current_module->connect(wire, sig);

24
frontends/blif/blifparse.cc
View file

@ -363,19 +363,19 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto no_latch_clock;
if (!strcmp(edge, "re"))
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
cell = module->addDff(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
else if (!strcmp(edge, "fe"))
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
cell = module->addDff(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else if (!strcmp(edge, "ah"))
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
cell = module->addDlatch(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
else if (!strcmp(edge, "al"))
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
cell = module->addDlatch(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else {
no_latch_clock:
if (dff_name.empty()) {
cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q));
cell = module->addFf(NEWER_ID, blif_wire(d), blif_wire(q));
} else {
cell = module->addCell(NEW_ID, dff_name);
cell = module->addCell(NEWER_ID, dff_name);
cell->setPort(ID::D, blif_wire(d));
cell->setPort(ID::Q, blif_wire(q));
}
@ -394,7 +394,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto error;
IdString celltype = RTLIL::escape_id(p);
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
RTLIL::Cell *cell = module->addCell(NEWER_ID, celltype);
RTLIL::Module *cell_mod = design->module(celltype);
dict<RTLIL::IdString, dict<int, SigBit>> cell_wideports_cache;
@ -441,7 +441,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (it.second.count(idx))
sig.append(it.second.at(idx));
else
sig.append(module->addWire(NEW_ID));
sig.append(module->addWire(NEWER_ID));
}
cell->setPort(it.first, sig);
@ -517,7 +517,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (sop_mode)
{
sopcell = module->addCell(NEW_ID, ID($sop));
sopcell = module->addCell(NEWER_ID, ID($sop));
sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
sopcell->parameters[ID::DEPTH] = 0;
sopcell->parameters[ID::TABLE] = RTLIL::Const();
@ -533,7 +533,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
}
else
{
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($lut));
cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
cell->setPort(ID::A, input_sig);
@ -586,8 +586,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
sopmode = (*output == '1');
if (!sopmode) {
SigSpec outnet = sopcell->getPort(ID::Y);
SigSpec tempnet = module->addWire(NEW_ID);
module->addNotGate(NEW_ID, tempnet, outnet);
SigSpec tempnet = module->addWire(NEWER_ID);
module->addNotGate(NEWER_ID, tempnet, outnet);
sopcell->setPort(ID::Y, tempnet);
}
} else

2
frontends/json/jsonparse.cc
View file

@ -549,7 +549,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
if (bitval_node->type == 'N') {
int bitidx = bitval_node->data_number;
if (signal_bits.count(bitidx) == 0)
signal_bits[bitidx] = module->addWire(NEW_ID);
signal_bits[bitidx] = module->addWire(NEWER_ID);
sig.append(signal_bits.at(bitidx));
} else
log_error("JSON cells node '%s' connection '%s' has invalid bit value on bit %d.\n",

52
frontends/liberty/liberty.cc
View file

@ -58,7 +58,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
int top = int(stack.size())-1;
if (0 <= top-1 && stack[top].type == 0 && stack[top-1].type == '!') {
token_t t = token_t(0, module->NotGate(NEW_ID, stack[top].sig));
token_t t = token_t(0, module->NotGate(NEWER_ID, stack[top].sig));
stack.pop_back();
stack.pop_back();
stack.push_back(t);
@ -66,7 +66,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
}
if (0 <= top-1 && stack[top].type == '\'' && stack[top-1].type == 0) {
token_t t = token_t(0, module->NotGate(NEW_ID, stack[top-1].sig));
token_t t = token_t(0, module->NotGate(NEWER_ID, stack[top-1].sig));
stack.pop_back();
stack.pop_back();
stack.push_back(t);
@ -81,7 +81,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
}
if (0 <= top-2 && stack[top-2].type == 1 && stack[top-1].type == '^' && stack[top].type == 1) {
token_t t = token_t(1, module->XorGate(NEW_ID, stack[top-2].sig, stack[top].sig));
token_t t = token_t(1, module->XorGate(NEWER_ID, stack[top-2].sig, stack[top].sig));
stack.pop_back();
stack.pop_back();
stack.pop_back();
@ -97,7 +97,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
}
if (0 <= top-1 && stack[top-1].type == 2 && stack[top].type == 2) {
token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-1].sig, stack[top].sig));
token_t t = token_t(2, module->AndGate(NEWER_ID, stack[top-1].sig, stack[top].sig));
stack.pop_back();
stack.pop_back();
stack.push_back(t);
@ -105,7 +105,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
}
if (0 <= top-2 && stack[top-2].type == 2 && (stack[top-1].type == '*' || stack[top-1].type == '&') && stack[top].type == 2) {
token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-2].sig, stack[top].sig));
token_t t = token_t(2, module->AndGate(NEWER_ID, stack[top-2].sig, stack[top].sig));
stack.pop_back();
stack.pop_back();
stack.pop_back();
@ -121,7 +121,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
}
if (0 <= top-2 && stack[top-2].type == 3 && (stack[top-1].type == '+' || stack[top-1].type == '|') && stack[top].type == 3) {
token_t t = token_t(3, module->OrGate(NEW_ID, stack[top-2].sig, stack[top].sig));
token_t t = token_t(3, module->OrGate(NEWER_ID, stack[top-2].sig, stack[top].sig));
stack.pop_back();
stack.pop_back();
stack.pop_back();
@ -183,11 +183,11 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
{
RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($tribuf));
cell->setParam(ID::WIDTH, GetSize(func));
cell->setPort(ID::A, func);
cell->setPort(ID::EN, module->NotGate(NEW_ID, three_state));
cell->setPort(ID::Y, module->addWire(NEW_ID));
cell->setPort(ID::EN, module->NotGate(NEWER_ID, three_state));
cell->setPort(ID::Y, module->addWire(NEWER_ID));
return cell->getPort(ID::Y);
}
@ -236,11 +236,11 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
}
}
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($_NOT_));
cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig);
cell = module->addCell(NEW_ID, "");
cell = module->addCell(NEWER_ID, "");
cell->setPort(ID::D, data_sig);
cell->setPort(ID::Q, iq_sig);
cell->setPort(ID::C, clk_sig);
@ -319,7 +319,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
}
}
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($_NOT_));
cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig);
@ -330,9 +330,9 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
if (clear_polarity == true || clear_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *inv = module->addCell(NEWER_ID, ID($_NOT_));
inv->setPort(ID::A, clear_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
inv->setPort(ID::Y, module->addWire(NEWER_ID));
if (clear_polarity == true)
clear_negative = inv->getPort(ID::Y);
@ -340,15 +340,15 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
clear_enable = inv->getPort(ID::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
RTLIL::Cell *data_gate = module->addCell(NEWER_ID, ID($_AND_));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, clear_negative);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
data_gate->setPort(ID::Y, data_sig = module->addWire(NEWER_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
RTLIL::Cell *enable_gate = module->addCell(NEWER_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, clear_enable);
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEWER_ID));
}
if (preset_sig.size() == 1)
@ -358,9 +358,9 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
if (preset_polarity == false || preset_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *inv = module->addCell(NEWER_ID, ID($_NOT_));
inv->setPort(ID::A, preset_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
inv->setPort(ID::Y, module->addWire(NEWER_ID));
if (preset_polarity == false)
preset_positive = inv->getPort(ID::Y);
@ -368,18 +368,18 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
preset_enable = inv->getPort(ID::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
RTLIL::Cell *data_gate = module->addCell(NEWER_ID, ID($_OR_));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, preset_positive);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
data_gate->setPort(ID::Y, data_sig = module->addWire(NEWER_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
RTLIL::Cell *enable_gate = module->addCell(NEWER_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, preset_enable);
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEWER_ID));
}
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell = module->addCell(NEWER_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell->setPort(ID::D, data_sig);
cell->setPort(ID::Q, iq_sig);
cell->setPort(ID::E, enable_sig);
@ -734,7 +734,7 @@ struct LibertyFrontend : public Frontend {
if (wi->port_input) {
for (auto wo : module->wires())
if (wo->port_output) {
RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2));
RTLIL::Cell *spec = module->addCell(NEWER_ID, ID($specify2));
spec->setParam(ID::SRC_WIDTH, wi->width);
spec->setParam(ID::DST_WIDTH, wo->width);
spec->setParam(ID::T_FALL_MAX, 1000);

46
frontends/verific/verific.cc
View file

@ -759,8 +759,8 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
if (inst->GetAsyncCond()->IsGnd()) {
module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
} else {
RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()));
RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal())));
RTLIL::SigSpec sig_set = module->And(NEWER_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()));
RTLIL::SigSpec sig_clr = module->And(NEWER_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEWER_ID, net_map_at(inst->GetAsyncVal())));
module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
}
return true;
@ -896,8 +896,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
if (inst->GetAsyncCond()->IsGnd()) {
cell = module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
} else {
RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()));
RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal())));
RTLIL::SigSpec sig_set = module->And(NEWER_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()));
RTLIL::SigSpec sig_clr = module->And(NEWER_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEWER_ID, net_map_at(inst->GetAsyncVal())));
cell = module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
}
import_attributes(cell->attributes, inst);
@ -1000,9 +1000,9 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
}
if (inst->Type() == OPER_REDUCE_NAND) {
Wire *tmp = module->addWire(NEW_ID);
Wire *tmp = module->addWire(NEWER_ID);
cell = module->addReduceAnd(inst_name, IN, tmp, SIGNED);
module->addNot(NEW_ID, tmp, net_map_at(inst->GetOutput()));
module->addNot(NEWER_ID, tmp, net_map_at(inst->GetOutput()));
import_attributes(cell->attributes, inst);
return true;
}
@ -1219,8 +1219,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
for (offset = 0; offset < GetSize(sig_acond); offset += width) {
for (width = 1; offset+width < GetSize(sig_acond); width++)
if (sig_acond[offset] != sig_acond[offset+width]) break;
RTLIL::SigSpec sig_set = module->Mux(NEW_ID, RTLIL::SigSpec(0, width), sig_adata.extract(offset, width), sig_acond[offset]);
RTLIL::SigSpec sig_clr = module->Mux(NEW_ID, RTLIL::SigSpec(0, width), module->Not(NEW_ID, sig_adata.extract(offset, width)), sig_acond[offset]);
RTLIL::SigSpec sig_set = module->Mux(NEWER_ID, RTLIL::SigSpec(0, width), sig_adata.extract(offset, width), sig_acond[offset]);
RTLIL::SigSpec sig_clr = module->Mux(NEWER_ID, RTLIL::SigSpec(0, width), module->Not(NEWER_ID, sig_adata.extract(offset, width)), sig_acond[offset]);
cell = module->addDlatchsr(module->uniquify(inst_name), net_map_at(inst->GetControl()), sig_set, sig_clr,
sig_d.extract(offset, width), sig_q.extract(offset, width));
import_attributes(cell->attributes, inst);
@ -1374,8 +1374,8 @@ void VerificImporter::merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBi
if (chunk.wire == nullptr || GetSize(sig_d) == 1)
continue;
SigSpec sig_q = module->addWire(NEW_ID, GetSize(sig_d));
RTLIL::Cell *new_ff = module->addDff(NEW_ID, clock, sig_d, sig_q, clock_pol);
SigSpec sig_q = module->addWire(NEWER_ID, GetSize(sig_d));
RTLIL::Cell *new_ff = module->addDff(NEWER_ID, clock, sig_d, sig_q, clock_pol);
if (verific_verbose)
log(" merging single-bit past_ffs into new %d-bit ff %s.\n", GetSize(sig_d), log_id(new_ff));
@ -2470,7 +2470,7 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const
if (s.is_wire()) {
s.as_wire()->attributes[ID::init] = init_value;
} else {
Wire *w = module->addWire(NEW_ID, GetSize(s));
Wire *w = module->addWire(NEWER_ID, GetSize(s));
w->attributes[ID::init] = init_value;
module->connect(s, w);
s = w;
@ -2478,14 +2478,14 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const
};
if (enable_sig != State::S1)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
sig_d = module->Mux(NEWER_ID, sig_q, sig_d, enable_sig);
if (disable_sig != State::S0) {
log_assert(GetSize(sig_q) == GetSize(init_value));
if (gclk) {
Wire *pre_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *post_q_w = module->addWire(NEW_ID, GetSize(sig_q));
Wire *pre_d = module->addWire(NEWER_ID, GetSize(sig_d));
Wire *post_q_w = module->addWire(NEWER_ID, GetSize(sig_q));
Const initval(State::Sx, GetSize(sig_q));
int offset = 0;
@ -2501,8 +2501,8 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const
if (!initval.is_fully_undef())
post_q_w->attributes[ID::init] = initval;
module->addMux(NEW_ID, sig_d, init_value, disable_sig, pre_d);
module->addMux(NEW_ID, post_q_w, init_value, disable_sig, sig_q);
module->addMux(NEWER_ID, sig_d, init_value, disable_sig, pre_d);
module->addMux(NEWER_ID, post_q_w, init_value, disable_sig, sig_q);
SigSpec post_q(post_q_w);
set_init_attribute(post_q);
@ -2529,7 +2529,7 @@ Cell *VerificClocking::addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec s
// FIXME: Adffe
if (enable_sig != State::S1)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
sig_d = module->Mux(NEWER_ID, sig_q, sig_d, enable_sig);
return module->addAdff(name, clock_sig, sig_arst, sig_d, sig_q, arst_value, posedge);
}
@ -2541,7 +2541,7 @@ Cell *VerificClocking::addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::Si
// FIXME: Dffsre
if (enable_sig != State::S1)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
sig_d = module->Mux(NEWER_ID, sig_q, sig_d, enable_sig);
return module->addDffsr(name, clock_sig, sig_set, sig_clr, sig_d, sig_q, posedge);
}
@ -2552,11 +2552,11 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::
// FIXME: Aldffe
if (enable_sig != State::S1)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
sig_d = module->Mux(NEWER_ID, sig_q, sig_d, enable_sig);
if (gclk) {
Wire *pre_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *post_q = module->addWire(NEW_ID, GetSize(sig_q));
Wire *pre_d = module->addWire(NEWER_ID, GetSize(sig_d));
Wire *post_q = module->addWire(NEWER_ID, GetSize(sig_q));
Const initval(State::Sx, GetSize(sig_q));
int offset = 0;
@ -2572,8 +2572,8 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::
if (!initval.is_fully_undef())
post_q->attributes[ID::init] = initval;
module->addMux(NEW_ID, sig_d, sig_adata, sig_aload, pre_d);
module->addMux(NEW_ID, post_q, sig_adata, sig_aload, sig_q);
module->addMux(NEWER_ID, sig_d, sig_adata, sig_aload, pre_d);
module->addMux(NEWER_ID, post_q, sig_adata, sig_aload, sig_q);
return module->addFf(name, pre_d, post_q);
}

90
frontends/verific/verificsva.cc
View file

@ -166,7 +166,7 @@ struct SvaFsm
if (disable_sig == State::S0)
disable_sig = sig;
else
disable_sig = module->Or(NEW_ID, disable_sig, sig);
disable_sig = module->Or(NEWER_ID, disable_sig, sig);
}
void popDisable()
@ -187,7 +187,7 @@ struct SvaFsm
if (throughout_sig == State::S1)
throughout_sig = sig;
else
throughout_sig = module->And(NEW_ID, throughout_sig, sig);
throughout_sig = module->And(NEWER_ID, throughout_sig, sig);
}
void popThroughout()
@ -232,7 +232,7 @@ struct SvaFsm
if (throughout_sig != State::S1) {
if (ctrl != State::S1)
ctrl = module->And(NEW_ID, throughout_sig, ctrl);
ctrl = module->And(NEWER_ID, throughout_sig, ctrl);
else
ctrl = throughout_sig;
}
@ -254,7 +254,7 @@ struct SvaFsm
if (throughout_sig != State::S1) {
if (ctrl != State::S1)
ctrl = module->And(NEW_ID, throughout_sig, ctrl);
ctrl = module->And(NEWER_ID, throughout_sig, ctrl);
else
ctrl = throughout_sig;
}
@ -287,19 +287,19 @@ struct SvaFsm
SigBit not_disable = State::S1;
if (disable_sig != State::S0)
not_disable = module->Not(NEW_ID, disable_sig);
not_disable = module->Not(NEWER_ID, disable_sig);
for (int i = 0; i < GetSize(nodes); i++)
{
Wire *w = module->addWire(NEW_ID);
Wire *w = module->addWire(NEWER_ID);
state_wire[i] = w;
state_sig[i] = w;
if (i == startNode)
state_sig[i] = module->Or(NEW_ID, state_sig[i], trigger_sig);
state_sig[i] = module->Or(NEWER_ID, state_sig[i], trigger_sig);
if (disable_sig != State::S0)
state_sig[i] = module->And(NEW_ID, state_sig[i], not_disable);
state_sig[i] = module->And(NEWER_ID, state_sig[i], not_disable);
}
}
@ -327,9 +327,9 @@ struct SvaFsm
SigBit ctrl = state_sig[node];
if (it.second != State::S1)
ctrl = module->And(NEW_ID, ctrl, it.second);
ctrl = module->And(NEWER_ID, ctrl, it.second);
state_sig[target] = module->Or(NEW_ID, state_sig[target], ctrl);
state_sig[target] = module->Or(NEWER_ID, state_sig[target], ctrl);
}
}
}
@ -342,7 +342,7 @@ struct SvaFsm
for (int i = 0; i < GetSize(nodes); i++) {
for (auto &it : nodes[i].edges)
activate_sig[it.first].append(module->And(NEW_ID, state_sig[i], it.second));
activate_sig[it.first].append(module->And(NEWER_ID, state_sig[i], it.second));
}
for (int i = 0; i < GetSize(nodes); i++) {
@ -351,7 +351,7 @@ struct SvaFsm
else if (GetSize(activate_sig[i]) == 1)
next_state_sig[i] = activate_sig[i];
else
next_state_sig[i] = module->ReduceOr(NEW_ID, activate_sig[i]);
next_state_sig[i] = module->ReduceOr(NEWER_ID, activate_sig[i]);
}
}
@ -360,7 +360,7 @@ struct SvaFsm
for (int i = 0; i < GetSize(nodes); i++)
{
if (next_state_sig[i] != State::S0) {
clocking.addDff(NEW_ID, next_state_sig[i], state_wire[i], State::S0);
clocking.addDff(NEWER_ID, next_state_sig[i], state_wire[i], State::S0);
} else {
module->connect(state_wire[i], State::S0);
}
@ -626,9 +626,9 @@ struct SvaFsm
if (sig_b == State::S1)
cond_eq_cache[key] = sig_a;
else if (sig_b == State::S0)
cond_eq_cache[key] = module->Not(NEW_ID, sig_a);
cond_eq_cache[key] = module->Not(NEWER_ID, sig_a);
else
cond_eq_cache[key] = module->Eq(NEW_ID, sig_a, sig_b);
cond_eq_cache[key] = module->Eq(NEWER_ID, sig_a, sig_b);
if (verific_verbose >= 2) {
log(" Cond: %s := %s == %s\n", log_signal(cond_eq_cache[key]),
@ -665,11 +665,11 @@ struct SvaFsm
for (auto &it : dnodes)
{
SvaDFsmNode &dnode = it.second;
dnode.ffoutwire = module->addWire(NEW_ID);
dnode.ffoutwire = module->addWire(NEWER_ID);
dnode.statesig = dnode.ffoutwire;
if (it.first == vector<int>{startNode})
dnode.statesig = module->Or(NEW_ID, dnode.statesig, trigger_sig);
dnode.statesig = module->Or(NEWER_ID, dnode.statesig, trigger_sig);
}
for (auto &it : dnodes)
@ -708,10 +708,10 @@ struct SvaFsm
module->connect(dnode.ffoutwire, State::S0);
} else
if (GetSize(dnode.nextstate) == 1) {
clocking.addDff(NEW_ID, dnode.nextstate, dnode.ffoutwire, State::S0);
clocking.addDff(NEWER_ID, dnode.nextstate, dnode.ffoutwire, State::S0);
} else {
SigSpec nextstate = module->ReduceOr(NEW_ID, dnode.nextstate);
clocking.addDff(NEW_ID, nextstate, dnode.ffoutwire, State::S0);
SigSpec nextstate = module->ReduceOr(NEWER_ID, dnode.nextstate);
clocking.addDff(NEWER_ID, nextstate, dnode.ffoutwire, State::S0);
}
}
@ -722,7 +722,7 @@ struct SvaFsm
else if (GetSize(accept_sig) == 1)
final_accept_sig = accept_sig;
else
final_accept_sig = module->ReduceOr(NEW_ID, accept_sig);
final_accept_sig = module->ReduceOr(NEWER_ID, accept_sig);
*accept_p = final_accept_sig;
}
@ -733,7 +733,7 @@ struct SvaFsm
else if (GetSize(reject_sig) == 1)
final_reject_sig = reject_sig;
else
final_reject_sig = module->ReduceOr(NEW_ID, reject_sig);
final_reject_sig = module->ReduceOr(NEWER_ID, reject_sig);
*reject_p = final_reject_sig;
}
}
@ -1135,14 +1135,14 @@ struct VerificSvaImporter
return parse_expression(inst->GetInput());
if (inst->Type() == PRIM_SVA_NOT)
return module->Not(NEW_ID, parse_expression(inst->GetInput()));
return module->Not(NEWER_ID, parse_expression(inst->GetInput()));
if (inst->Type() == PRIM_SVA_SEQ_OR || inst->Type() == PRIM_SVA_OR)
return module->Or(NEW_ID, parse_expression(inst->GetInput1()), parse_expression(inst->GetInput2()));
return module->Or(NEWER_ID, parse_expression(inst->GetInput1()), parse_expression(inst->GetInput2()));
if (inst->Type() == PRIM_SVA_SEQ_AND || inst->Type() == PRIM_SVA_AND || inst->Type() == PRIM_SVA_INTERSECT ||
inst->Type() == PRIM_SVA_WITHIN || inst->Type() == PRIM_SVA_THROUGHOUT || inst->Type() == PRIM_SVA_SEQ_CONCAT)
return module->And(NEW_ID, parse_expression(inst->GetInput1()), parse_expression(inst->GetInput2()));
return module->And(NEWER_ID, parse_expression(inst->GetInput1()), parse_expression(inst->GetInput2()));
log_abort();
}
@ -1364,7 +1364,7 @@ struct VerificSvaImporter
int node = fsm.createNode(start_node);
SigBit cond = parse_expression(body_net);
SigBit not_cond = module->Not(NEW_ID, cond);
SigBit not_cond = module->Not(NEWER_ID, cond);
for (int i = 0; i < sva_low; i++)
{
@ -1526,7 +1526,7 @@ struct VerificSvaImporter
if (clocking.cond_net != nullptr) {
trig = importer->net_map_at(clocking.cond_net);
if (!clocking.cond_pol)
trig = module->Not(NEW_ID, trig);
trig = module->Not(NEWER_ID, trig);
} else {
trig = State::S1;
}
@ -1594,21 +1594,21 @@ struct VerificSvaImporter
if (clocking.cond_net != nullptr) {
trig = importer->net_map_at(clocking.cond_net);
if (!clocking.cond_pol)
trig = module->Not(NEW_ID, trig);
trig = module->Not(NEWER_ID, trig);
}
if (inst == nullptr)
{
if (trig != State::S1) {
if (accept_p != nullptr)
*accept_p = module->And(NEW_ID, trig, importer->net_map_at(net));
*accept_p = module->And(NEWER_ID, trig, importer->net_map_at(net));
if (reject_p != nullptr)
*reject_p = module->And(NEW_ID, trig, module->Not(NEW_ID, importer->net_map_at(net)));
*reject_p = module->And(NEWER_ID, trig, module->Not(NEWER_ID, importer->net_map_at(net)));
} else {
if (accept_p != nullptr)
*accept_p = importer->net_map_at(net);
if (reject_p != nullptr)
*reject_p = module->Not(NEW_ID, importer->net_map_at(net));
*reject_p = module->Not(NEWER_ID, importer->net_map_at(net));
}
}
else
@ -1652,7 +1652,7 @@ struct VerificSvaImporter
}
SigBit until_sig = until_net ? parse_expression(until_net) : RTLIL::S0;
SigBit not_until_sig = module->Not(NEW_ID, until_sig);
SigBit not_until_sig = module->Not(NEWER_ID, until_sig);
antecedent_fsm.createEdge(node, node, not_until_sig);
antecedent_fsm.createLink(node, antecedent_fsm.acceptNode, until_with ? State::S1 : not_until_sig);
@ -1732,7 +1732,7 @@ struct VerificSvaImporter
}
}
RTLIL::IdString root_name = module->uniquify(importer->mode_names || is_user_declared ? RTLIL::escape_id(root->Name()) : NEW_ID);
RTLIL::IdString root_name = module->uniquify(importer->mode_names || is_user_declared ? RTLIL::escape_id(root->Name()) : NEWER_ID);
// parse SVA sequence into trigger signal
@ -1745,7 +1745,7 @@ struct VerificSvaImporter
parser_error(stringf("Failed to parse SVA clocking"), root);
if (mode_assert || mode_assume) {
reject_bit = module->Not(NEW_ID, parse_expression(root->GetInput()));
reject_bit = module->Not(NEWER_ID, parse_expression(root->GetInput()));
} else {
accept_bit = parse_expression(root->GetInput());
}
@ -1768,16 +1768,16 @@ struct VerificSvaImporter
sig_a_q = sig_a;
sig_en_q = sig_en;
} else {
sig_a_q = module->addWire(NEW_ID);
sig_en_q = module->addWire(NEW_ID);
clocking.addDff(NEW_ID, sig_a, sig_a_q, State::S0);
clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);
sig_a_q = module->addWire(NEWER_ID);
sig_en_q = module->addWire(NEWER_ID);
clocking.addDff(NEWER_ID, sig_a, sig_a_q, State::S0);
clocking.addDff(NEWER_ID, sig_en, sig_en_q, State::S0);
}
// accept in disable case
if (clocking.disable_sig != State::S0)
sig_a_q = module->Or(NEW_ID, sig_a_q, clocking.disable_sig);
sig_a_q = module->Or(NEWER_ID, sig_a_q, clocking.disable_sig);
// generate fair/live cell
@ -1806,8 +1806,8 @@ struct VerificSvaImporter
}
else
{
SigBit sig_a = module->Not(NEW_ID, reject_bit);
SigBit sig_en = module->Or(NEW_ID, accept_bit, reject_bit);
SigBit sig_a = module->Not(NEWER_ID, reject_bit);
SigBit sig_en = module->Or(NEWER_ID, accept_bit, reject_bit);
// add final FF stage
@ -1817,10 +1817,10 @@ struct VerificSvaImporter
sig_a_q = sig_a;
sig_en_q = sig_en;
} else {
sig_a_q = module->addWire(NEW_ID);
sig_en_q = module->addWire(NEW_ID);
clocking.addDff(NEW_ID, sig_a, sig_a_q, State::S0);
clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);
sig_a_q = module->addWire(NEWER_ID);
sig_en_q = module->addWire(NEWER_ID);
clocking.addDff(NEWER_ID, sig_a, sig_a_q, State::S0);
clocking.addDff(NEWER_ID, sig_en, sig_en_q, State::S0);
}
// generate assert/assume/cover cell