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patch: signorm, move
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parent
b7ea32dbee
commit
d2ae9b48e4
3 changed files with 51 additions and 22 deletions
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@ -13,7 +13,7 @@ struct TestPatchPass : public Pass {
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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(void) args;
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design->bufNormalize();
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design->sigNormalize();
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for (auto module : design->selected_modules()) {
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for (auto cell : module->selected_cells()) {
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if (cell->type == ID($add)) {
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@ -21,12 +21,13 @@ struct TestPatchPass : public Pass {
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patcher.mod = module;
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patcher.map = SigMap(module);
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RTLIL::Cell* sub = patcher.addCell(NEW_ID, ID($sub));
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sub->connections_ = cell->connections();
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// sub->connections_ = cell->connections();
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sub->parameters = cell->parameters;
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sub->setPort(ID::A, cell->getPort(ID::A));
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sub->setPort(ID::B, cell->getPort(ID::B));
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sub->setPort(ID::Y, cell->getPort(ID::Y));
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patcher.patch();
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sub->connections_[ID::A] = cell->getPort(ID::A);
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sub->connections_[ID::B] = cell->getPort(ID::B);
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sub->connections_[ID::Y] = cell->getPort(ID::Y);
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log_cell(sub);
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patcher.patch(cell, sub);
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}
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}
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}
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