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Various cleanups in xilinx techlib

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This commit is contained in:
Clifford Wolf 2015-01-18 19:43:54 +01:00
parent 8d295730e5
commit d29d26f882
7 changed files with 110 additions and 9 deletions
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6
techlibs/xilinx/Makefile.inc
View file

@ -1,9 +1,9 @@
OBJS += techlibs/xilinx/synth_xilinx.o
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))

0
techlibs/xilinx/arith.v → techlibs/xilinx/arith_map.v
View file

34
techlibs/xilinx/brams.txt
View file

@ -23,6 +23,30 @@ bram $__XILINX_RAMB18_SDP
clkpol 2 3
endbram
bram $__XILINX_RAMB36_TDP
abits 10 @a10d36
dbits 36 @a10d36
abits 11 @a11d18
dbits 18 @a11d18
abits 12 @a12d9
dbits 9 @a12d9
abits 13 @a13d4
dbits 4 @a13d4
abits 14 @a14d2
dbits 2 @a14d2
abits 15 @a15d1
dbits 1 @a15d1
groups 2
ports 1 1
wrmode 0 1
enable 0 4 @a10d36
enable 0 2 @a11d18
enable 0 1 @a12d9 @a13d4 @a14d2 @a15d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB18_TDP
abits 10 @a10d18
dbits 18 @a10d18
@ -48,6 +72,7 @@ match $__XILINX_RAMB36_SDP
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
or_next_if_better
endmatch
@ -55,6 +80,15 @@ match $__XILINX_RAMB18_SDP
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
or_next_if_better
endmatch
match $__XILINX_RAMB36_TDP
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
or_next_if_better
endmatch

65
techlibs/xilinx/brams.v → techlibs/xilinx/brams_map.v
View file

@ -123,6 +123,71 @@ endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS);
wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS);
wire [7:0] B1EN_8 = B1EN;
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB36E1 #(
.RAM_MODE("TDP"),
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
) _TECHMAP_REPLACE_ (
.DIADI(32'd0),
.DIPADIP(4'd0),
.DOADO(DO[31:0]),
.DOPADOP(DOP[3:0]),
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
.ENARDEN(|1),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(4'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_16),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN_8)
);
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 18;

0
techlibs/xilinx/cells.v → techlibs/xilinx/cells_map.v
View file

12
techlibs/xilinx/synth_xilinx.cc
View file

@ -80,13 +80,13 @@ struct SynthXilinxPass : public Pass {
log("\n");
log(" bram:\n");
log(" memory_bram -rules +/xilinx/brams.txt\n");
log(" techmap -map +/xilinx/brams.v\n");
log(" techmap -map +/xilinx/brams_map.v\n");
log("\n");
log(" fine:\n");
log(" opt -fast -full\n");
log(" memory_map\n");
log(" opt -full\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith.v\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
log(" opt -fast\n");
log("\n");
log(" map_luts:\n");
@ -94,7 +94,7 @@ struct SynthXilinxPass : public Pass {
log(" clean\n");
log("\n");
log(" map_cells:\n");
log(" techmap -map +/xilinx/cells.v\n");
log(" techmap -map +/xilinx/cells_map.v\n");
log(" clean\n");
log("\n");
log(" edif:\n");
@ -169,7 +169,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "bram"))
{
Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
Pass::call(design, "techmap -map +/xilinx/brams.v");
Pass::call(design, "techmap -map +/xilinx/brams_map.v");
}
if (check_label(active, run_from, run_to, "fine"))
@ -177,7 +177,7 @@ struct SynthXilinxPass : public Pass {
Pass::call(design, "opt -fast -full");
Pass::call(design, "memory_map");
Pass::call(design, "opt -full");
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith.v");
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
Pass::call(design, "opt -fast");
}
@ -189,7 +189,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_cells"))
{
Pass::call(design, "techmap -map +/xilinx/cells.v");
Pass::call(design, "techmap -map +/xilinx/cells_map.v");
Pass::call(design, "clean");
}

2
techlibs/xilinx/tests/bram1.sh
View file

@ -56,6 +56,8 @@ echo "Testing..."
${MAKE:-make} -f bram1.mk
echo
echo "Used rules:" $(grep -h 'Selected rule.*with efficiency' bram1_*/synth.log | gawk '{ print $3; }' | sort -u)
echo "Cleaning up..."
rm -rf bram1_cmp bram1.mk bram1_[0-9]*/