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Refactor common parts of SAT-using optimizations into a helper.
This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization
This commit is contained in:
Marcelina Kościelnicka
parent
d8fcf1ab25
commit
d25b9088c8
7 changed files with 224 additions and 153 deletions
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@ -380,9 +380,11 @@ struct ModWalker
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}
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}
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ModWalker(RTLIL::Design *design) : design(design), module(NULL)
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ModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)
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{
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ct.setup(design);
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ct.setup(design);
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if (module)
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setup(module);
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}
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void setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)
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102
kernel/qcsat.cc
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102
kernel/qcsat.cc
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@ -0,0 +1,102 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/qcsat.h"
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USING_YOSYS_NAMESPACE
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std::vector<int> QuickConeSat::importSig(SigSpec sig)
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{
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sig = modwalker.sigmap(sig);
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for (auto bit : sig)
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bits_queue.insert(bit);
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return satgen.importSigSpec(sig);
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}
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int QuickConeSat::importSigBit(SigBit bit)
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{
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bit = modwalker.sigmap(bit);
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bits_queue.insert(bit);
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return satgen.importSigBit(bit);
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}
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void QuickConeSat::prepare()
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{
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while (!bits_queue.empty())
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{
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pool<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, bits_queue);
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for (auto bit : bits_queue)
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if (bit.wire && bit.wire->get_bool_attribute(ID::onehot) && !imported_onehot.count(bit.wire))
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{
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std::vector<int> bits = satgen.importSigSpec(bit.wire);
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for (int i : bits)
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for (int j : bits)
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if (i != j)
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ez->assume(ez->NOT(i), j);
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imported_onehot.insert(bit.wire);
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}
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bits_queue.clear();
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for (auto &pbit : portbits)
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{
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if (imported_cells.count(pbit.cell))
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continue;
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if (cell_complexity(pbit.cell) > max_cell_complexity)
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continue;
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if (max_cell_outs && GetSize(modwalker.cell_outputs[pbit.cell]) > max_cell_outs)
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continue;
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auto &inputs = modwalker.cell_inputs[pbit.cell];
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bits_queue.insert(inputs.begin(), inputs.end());
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satgen.importCell(pbit.cell);
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imported_cells.insert(pbit.cell);
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}
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if (max_cell_count && GetSize(imported_cells) > max_cell_count)
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break;
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}
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}
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int QuickConeSat::cell_complexity(RTLIL::Cell *cell)
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{
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if (cell->type.in(ID($concat), ID($slice), ID($pos), ID($_BUF_)))
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return 0;
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if (cell->type.in(ID($not), ID($and), ID($or), ID($xor), ID($xnor),
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ID($reduce_and), ID($reduce_or), ID($reduce_xor),
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ID($reduce_xnor), ID($reduce_bool),
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ID($logic_not), ID($logic_and), ID($logic_or),
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ID($eq), ID($ne), ID($eqx), ID($nex), ID($fa),
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ID($mux), ID($pmux), ID($lut), ID($sop),
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ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_),
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ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_),
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ID($_MUX_), ID($_NMUX_), ID($_MUX4_), ID($_MUX8_), ID($_MUX16_),
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ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
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return 1;
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if (cell->type.in(ID($neg), ID($add), ID($sub), ID($alu), ID($lcu),
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ID($lt), ID($le), ID($gt), ID($ge)))
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return 2;
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if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
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return 3;
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if (cell->type.in(ID($mul), ID($macc), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
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return 4;
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// Unknown cell.
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return 5;
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}
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76
kernel/qcsat.h
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76
kernel/qcsat.h
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@ -0,0 +1,76 @@
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/* -*- c++ -*-
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef QCSAT_H
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#define QCSAT_H
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#include "kernel/satgen.h"
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#include "kernel/modtools.h"
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YOSYS_NAMESPACE_BEGIN
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// This is a helper class meant for easy construction of quick SAT queries
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// to a combinatorial input cone of some set of signals, meant for SAT-based
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// optimizations. Various knobs are provided to set just how much of the
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// cone should be included in the model — since this class is meant for
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// optimization, it should not be a correctness problem when some cells are
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// skipped and the solver spuriously returns SAT with a solution that
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// cannot exist in reality due to skipped constraints (ie. only UNSAT results
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// from this class should be considered binding).
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struct QuickConeSat {
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ModWalker &modwalker;
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ezSatPtr ez;
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SatGen satgen;
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// The effort level knobs.
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// The maximum "complexity level" of cells that will be imported.
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// - 1: bitwise operations, muxes, equality comparisons, lut, sop, fa
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// - 2: addition, subtraction, greater/less than comparisons, lcu
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// - 3: shifts
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// - 4: multiplication, division, power
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int max_cell_complexity = 2;
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// The maximum number of cells to import, or 0 for no limit.
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int max_cell_count = 0;
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// If non-0, skip importing cells with more than this number of output bits.
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int max_cell_outs = 0;
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// Internal state.
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pool<RTLIL::Cell*> imported_cells;
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pool<RTLIL::Wire*> imported_onehot;
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pool<RTLIL::SigBit> bits_queue;
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QuickConeSat(ModWalker &modwalker) : modwalker(modwalker), ez(), satgen(ez.get(), &modwalker.sigmap) {}
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// Imports a signal into the SAT solver, queues its input cone to be
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// imported in the next prepare() call.
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std::vector<int> importSig(SigSpec sig);
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int importSigBit(SigBit bit);
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// Imports the input cones of all previously importSig'd signals into
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// the SAT solver.
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void prepare();
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// Returns the "complexity level" of a given cell.
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static int cell_complexity(RTLIL::Cell *cell);
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};
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YOSYS_NAMESPACE_END
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#endif
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