mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-16 19:05:47 +00:00
Code Activity

Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff()

Browse source
This commit is contained in:
Robert O'Callahan 2025-09-17 03:23:52 +00:00
parent b95549b469
commit d24488d3a5
32 changed files with 61 additions and 51 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/sat/sim.cc
View file

@ -308,7 +308,7 @@ struct SimInstance
}
}
if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
FfData ff_data(nullptr, cell);
ff_state_t ff;
ff.past_d = Const(State::Sx, ff_data.width);
@ -1017,7 +1017,7 @@ struct SimInstance
dict<Wire*,bool> registers;
for (auto cell : module->cells())
{
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (cell->is_builtin_ff()) {
FfData ff_data(nullptr, cell);
SigSpec q = sigmap(ff_data.sig_q);
if (q.is_wire() && signal_database.count(q.as_wire()) != 0) {