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Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff()

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This commit is contained in:
Robert O'Callahan 2025-09-17 03:23:52 +00:00
parent b95549b469
commit d24488d3a5
32 changed files with 61 additions and 51 deletions
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4
passes/cmds/check.cc
View file

@ -285,7 +285,7 @@ struct CheckPass : public Pass {
}
if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \
|| RTLIL::builtin_ff_cell_types().count(cell->type)) {
|| cell->is_builtin_ff()) {
if (!edges_db.add_edges_from_cell(cell))
coarsened_cells.insert(cell);
}
@ -426,7 +426,7 @@ struct CheckPass : public Pass {
{
for (auto cell : module->cells())
{
if (RTLIL::builtin_ff_cell_types().count(cell->type) == 0)
if (cell->is_builtin_ff() == 0)
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))

2
passes/cmds/clean_zerowidth.cc
View file

@ -73,7 +73,7 @@ struct CleanZeroWidthPass : public Pass {
cell->unsetPort(it.first);
}
}
} else if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
} else if (cell->is_builtin_ff()) {
// Coarse FF cells: remove if WIDTH == 0 (no outputs).
// This will also trigger on fine cells, so use the Q port
// width instead of actual WIDTH parameter.

4
passes/cmds/dft_tag.cc
View file

@ -430,7 +430,7 @@ struct DftTagWorker {
return;
}
if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
FfData ff(&initvals, cell);
if (ff.has_clk || ff.has_gclk)
@ -686,7 +686,7 @@ struct DftTagWorker {
return;
}
if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
FfData ff(&initvals, cell);
// TODO handle some more variants
if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {

2
passes/cmds/future.cc
View file

@ -85,7 +85,7 @@ struct FutureWorker {
if (found_driver->second.size() > 1)
log_error("Found multiple drivers for future_ff target signal %s\n", log_signal(bit));
auto driver = *found_driver->second.begin();
if (!RTLIL::builtin_ff_cell_types().count(driver.cell->type) && driver.cell->type != ID($anyinit))
if (!driver.cell->is_builtin_ff() && driver.cell->type != ID($anyinit))
log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), log_id(driver.cell->type));
FfData ff(&initvals, driver.cell);

2
passes/cmds/setundef.cc
View file

@ -364,7 +364,7 @@ struct SetundefPass : public Pass {
for (auto cell : module->cells())
{
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))

2
passes/cmds/timeest.cc
View file

@ -88,7 +88,7 @@ struct EstimateSta {
for (auto cell : m->cells()) {
SigSpec launch, sample;
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (cell->is_builtin_ff()) {
// collect launch and sample points for FF cell
FfData ff(nullptr, cell);
if (!ff.has_clk) {

4
passes/cmds/xprop.cc
View file

@ -302,7 +302,7 @@ struct XpropWorker
return;
}
if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
FfData ff(&initvals, cell);
if (cell->type != ID($anyinit))
@ -853,7 +853,7 @@ struct XpropWorker
return;
}
if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
FfData ff(&initvals, cell);
if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {