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Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff()

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This commit is contained in:
Robert O'Callahan 2025-09-17 03:23:52 +00:00
parent b95549b469
commit d24488d3a5
32 changed files with 61 additions and 51 deletions
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2
kernel/celledges.cc
View file

@ -447,7 +447,7 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
return true;
}
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (cell->is_builtin_ff()) {
ff_op(this, cell);
return true;
}

2
kernel/cost.cc
View file

@ -145,7 +145,7 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
if (design_ && design_->module(cell->type) && cell->parameters.empty()) {
log_debug("%s is a module, recurse\n", cell->name.c_str());
return get(design_->module(cell->type));
} else if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
} else if (cell->is_builtin_ff()) {
log_assert(cell->hasPort(ID::Q) && "Weird flip flop");
log_debug("%s is ff\n", cell->name.c_str());
return cell->getParam(ID::WIDTH).as_int();

2
kernel/ffmerge.cc
View file

@ -335,7 +335,7 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_)
}
for (auto cell : module->cells()) {
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (cell->is_builtin_ff()) {
if (cell->hasPort(ID::D)) {
SigSpec d = (*sigmap)(cell->getPort(ID::D));
for (int i = 0; i < GetSize(d); i++)

2
kernel/functional.cc
View file

@ -605,7 +605,7 @@ private:
}
Node node = handle_memory(mem);
factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node);
} else if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
} else if (cell->is_builtin_ff()) {
FfData ff(&ff_initvals, cell);
if (!ff.has_gclk)
log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. "

10
kernel/rtlil.cc
View file

@ -87,7 +87,7 @@ static_assert(check_well_known_id_order());
dict<std::string, std::string> RTLIL::constpad;
const pool<IdString> &RTLIL::builtin_ff_cell_types() {
static const pool<IdString> &builtin_ff_cell_types_internal() {
static const pool<IdString> res = {
ID($sr),
ID($ff),
@ -238,6 +238,10 @@ const pool<IdString> &RTLIL::builtin_ff_cell_types() {
return res;
}
const pool<IdString> &RTLIL::builtin_ff_cell_types() {
return builtin_ff_cell_types_internal();
}
#define check(condition) log_assert(condition && "malformed Const union")
const Const::bitvectype& Const::get_bits() const {
@ -4497,6 +4501,10 @@ bool RTLIL::Cell::is_mem_cell() const
return type.in(ID($mem), ID($mem_v2)) || has_memid();
}
bool RTLIL::Cell::is_builtin_ff() const {
return builtin_ff_cell_types_internal().count(type) > 0;
}
RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
{
wire = bit.wire;

2
kernel/rtlil.h
View file

@ -556,6 +556,7 @@ template <> struct IDMacroHelper<-1> {
namespace RTLIL {
extern dict<std::string, std::string> constpad;
[[deprecated("Call cell->is_builtin_ff() instead")]]
const pool<IdString> &builtin_ff_cell_types();
static inline std::string escape_id(const std::string &str) {
@ -2147,6 +2148,7 @@ public:
bool has_memid() const;
bool is_mem_cell() const;
bool is_builtin_ff() const;
};
struct RTLIL::CaseRule : public RTLIL::AttrObject

2
kernel/satgen.cc
View file

@ -1202,7 +1202,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
return true;
}
if (timestep > 0 && (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)))
if (timestep > 0 && (cell->is_builtin_ff() || cell->type == ID($anyinit)))
{
FfData ff(nullptr, cell);