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reconsidering unset

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This commit is contained in:
Emil J. Tywoniak 2024-06-20 16:43:45 +02:00
parent 76102f0bc5
commit d2107a9ee4
4 changed files with 17 additions and 15 deletions
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8
passes/opt/opt_expr.cc
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@ -408,6 +408,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {
log("%s\n", cell->name.c_str());
log_cell(cell, "inner ");
if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
@ -2305,6 +2307,9 @@ struct OptExprPass : public Pass {
CellTypes ct(design);
for (auto module : design->selected_modules())
{
for (auto cell : module->cells()) {
log_cell(cell, "start ");
}
log("Optimizing module %s.\n", log_id(module));
if (undriven) {
@ -2313,6 +2318,9 @@ struct OptExprPass : public Pass {
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
}
for (auto cell : module->cells()) {
log_cell(cell, "mid ");
}
do {
do {

4
passes/techmap/alumacc.cc
View file

@ -240,12 +240,8 @@ struct AlumaccWorker
for (int i = 0; i < GetSize(n->macc.ports); i++)
{
log("ports: size %d\n", n->macc.ports.size());
auto &port = n->macc.ports[i];
log("ports 2: size %d\n", port.in_b.size());
log("uuh: count %d\n", sig_macc.count(port.in_a));
log("%s\n", log_signal(port.in_a));
if (GetSize(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
continue;