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Added Xilinx test case for initialized brams

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This commit is contained in:
Clifford Wolf 2015-04-06 13:03:37 +02:00
parent 4389d9306e
commit d19866615b
4 changed files with 80 additions and 0 deletions
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24
techlibs/xilinx/tests/bram2.v Normal file
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module myram(
input rd_clk,
input [ 7:0] rd_addr,
output reg [15:0] rd_data,
input wr_clk,
input wr_enable,
input [ 7:0] wr_addr,
input [15:0] wr_data
);
reg [15:0] memory [0:255];
integer i;
initial begin
for (i = 0; i < 256; i = i+1)
memory[i] = i;
end
always @(posedge rd_clk)
rd_data <= memory[rd_addr];
always @(posedge wr_clk)
if (wr_enable)
memory[wr_addr] <= wr_data;
endmodule