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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-09-22 17:47:23 -07:00 • committed by GitHub
commit d16ca47549
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21 changed files with 274 additions and 120 deletions
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35
passes/techmap/abc.cc
View file

@ -295,6 +295,7 @@ struct RunAbcState {
struct AbcModuleState {
RunAbcState run_abc;
int state_index;
int map_autoidx = 0;
std::vector<RTLIL::SigBit> signal_bits;
dict<RTLIL::SigBit, int> signal_map;
@ -309,8 +310,8 @@ struct AbcModuleState {
int undef_bits_lost = 0;
AbcModuleState(const AbcConfig &config, FfInitVals &initvals)
: run_abc(config), initvals(initvals) {}
AbcModuleState(const AbcConfig &config, FfInitVals &initvals, int state_index)
: run_abc(config), state_index(state_index), initvals(initvals) {}
AbcModuleState(AbcModuleState&&) = delete;
int map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1);
@ -2458,7 +2459,7 @@ struct AbcPass : public Pass {
std::vector<RTLIL::Cell*> cells = mod->selected_cells();
assign_cell_connection_ports(mod, {&cells}, assign_map);
AbcModuleState state(config, initvals);
AbcModuleState state(config, initvals, 0);
state.prepare_module(design, mod, assign_map, cells, dff_mode, clk_str);
ConcurrentStack<AbcProcess> process_pool;
state.run_abc.run(process_pool);
@ -2634,7 +2635,6 @@ struct AbcPass : public Pass {
int num_worker_threads = ThreadPool::pool_size(1, max_threads);
ConcurrentQueue<std::unique_ptr<AbcModuleState>> work_queue(num_worker_threads);
ConcurrentQueue<std::unique_ptr<AbcModuleState>> work_finished_queue;
int work_finished_count = 0;
ConcurrentStack<AbcProcess> process_pool;
ThreadPool worker_threads(num_worker_threads, [&](int){
while (std::optional<std::unique_ptr<AbcModuleState>> work =
@ -2644,15 +2644,25 @@ struct AbcPass : public Pass {
work_finished_queue.push_back(std::move(*work));
}
});
int state_index = 0;
int next_state_index_to_process = 0;
std::vector<std::unique_ptr<AbcModuleState>> work_finished_by_index;
work_finished_by_index.resize(assigned_cells.size());
int work_finished_count = 0;
for (auto &it : assigned_cells) {
// Process ABC results that have already finished before queueing another ABC.
// This should keep our memory usage down.
// Make sure we process the results in the order we expect. When we can
// process results before the next ABC run, do so, to keep memory usage low(er).
while (std::optional<std::unique_ptr<AbcModuleState>> work =
work_finished_queue.try_pop_front()) {
(*work)->extract(assign_map, design, mod);
work_finished_by_index[(*work)->state_index] = std::move(*work);
++work_finished_count;
}
std::unique_ptr<AbcModuleState> state = std::make_unique<AbcModuleState>(config, initvals);
while (work_finished_by_index[next_state_index_to_process] != nullptr) {
work_finished_by_index[next_state_index_to_process]->extract(assign_map, design, mod);
work_finished_by_index[next_state_index_to_process] = nullptr;
++next_state_index_to_process;
}
std::unique_ptr<AbcModuleState> state = std::make_unique<AbcModuleState>(config, initvals, state_index++);
state->clk_polarity = std::get<0>(it.first);
state->clk_sig = assign_map(std::get<1>(it.first));
state->en_polarity = std::get<2>(it.first);
@ -2671,12 +2681,17 @@ struct AbcPass : public Pass {
}
}
work_queue.close();
while (work_finished_count < static_cast<int>(assigned_cells.size())) {
while (work_finished_count < GetSize(assigned_cells)) {
std::optional<std::unique_ptr<AbcModuleState>> work =
work_finished_queue.pop_front();
(*work)->extract(assign_map, design, mod);
work_finished_by_index[(*work)->state_index] = std::move(*work);
++work_finished_count;
}
while (next_state_index_to_process < GetSize(work_finished_by_index)) {
work_finished_by_index[next_state_index_to_process]->extract(assign_map, design, mod);
work_finished_by_index[next_state_index_to_process] = nullptr;
++next_state_index_to_process;
}
}
if (config.cleanup) {

9
passes/techmap/techmap.cc
View file

@ -1042,6 +1042,10 @@ struct TechmapPass : public Pass {
log(" -dont_map <celltype>\n");
log(" leave the given cell type unmapped by ignoring any mapping rules for it\n");
log("\n");
log(" -relativeshare\n");
log(" use paths relative to share directory for source locations\n");
log(" where possible (experimental).\n");
log("\n");
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
log("match cells with a type that match the text value of this attribute. Otherwise\n");
log("the module name will be used to match the cell. Multiple space-separated cell\n");
@ -1195,6 +1199,11 @@ struct TechmapPass : public Pass {
verilog_frontend += " -I " + args[++argidx];
continue;
}
if (args[argidx] == "-relativeshare") {
verilog_frontend += " -relativeshare";
log_experimental("techmap -relativeshare");
continue;
}
if (args[argidx] == "-assert") {
worker.assert_mode = true;
continue;