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Add new tests.

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SergeyDegtyar 2019-08-30 09:45:33 +03:00
parent eb0a5b2293
commit d144748401
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read_verilog alu.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 62 t:SB_CARRY
select -assert-count 32 t:SB_DFF
select -assert-count 655 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D