mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-23 07:32:32 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-08 23:40:51 +02:00
parent 1a8a95b472
commit d13dfc21f4
32 changed files with 1348 additions and 769 deletions
Download patch file Download diff file Expand all files Collapse all files

28
passes/techmap/abc9_ops.cc
View file

@ -1298,8 +1298,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
SigBit D = mapped_cell->getPort(ID::D);
SigBit Q = mapped_cell->getPort(ID::Q);
if (D.wire)
D.wire = module->wires_.at(remap_name(D.wire->name));
Q.wire = module->wires_.at(remap_name(Q.wire->name));
D.wire = module->wire(remap_name(D.wire->name));
Q.wire = module->wire(remap_name(Q.wire->name));
module->connect(Q, D);
continue;
}
@ -1341,8 +1341,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// If a driver couldn't be found (could be from PI or box CI)
// then implement using a LUT
RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name)),
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::SigBit(module->wire(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wire(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
bit2sinks[cell->getPort(ID::A)].push_back(cell);
cell_stats[ID($lut)]++;
@ -1365,7 +1365,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
continue;
//log_assert(c.width == 1);
if (c.wire)
c.wire = module->wires_.at(remap_name(c.wire->name));
c.wire = module->wire(remap_name(c.wire->name));
newsig.append(c);
}
cell->setPort(mapped_conn.first, newsig);
@ -1392,9 +1392,9 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
SigBit I = mapped_cell->getPort(ID(i));
SigBit O = mapped_cell->getPort(ID(o));
if (I.wire)
I.wire = module->wires_.at(remap_name(I.wire->name));
I.wire = module->wire(remap_name(I.wire->name));
log_assert(O.wire);
O.wire = module->wires_.at(remap_name(O.wire->name));
O.wire = module->wire(remap_name(O.wire->name));
module->connect(O, I);
continue;
}
@ -1434,7 +1434,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
old_q = existing_cell->getPort(port_name);
}
auto new_q = outputs[0];
new_q.wire = module->wires_.at(remap_name(new_q.wire->name));
new_q.wire = module->wire(remap_name(new_q.wire->name));
module->connect(old_q, new_q);
}
else {
@ -1467,7 +1467,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
continue;
//log_assert(c.width == 1);
if (c.wire)
c.wire = module->wires_.at(remap_name(c.wire->name));
c.wire = module->wire(remap_name(c.wire->name));
newsig.append(c);
}
@ -1490,14 +1490,14 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
if (!conn.first.is_fully_const()) {
std::vector<RTLIL::SigChunk> chunks = conn.first.chunks();
for (auto &c : chunks)
c.wire = module->wires_.at(remap_name(c.wire->name));
c.wire = module->wire(remap_name(c.wire->name));
conn.first = std::move(chunks);
}
if (!conn.second.is_fully_const()) {
std::vector<RTLIL::SigChunk> chunks = conn.second.chunks();
for (auto &c : chunks)
if (c.wire)
c.wire = module->wires_.at(remap_name(c.wire->name));
c.wire = module->wire(remap_name(c.wire->name));
conn.second = std::move(chunks);
}
module->connect(conn);
@ -1564,8 +1564,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
RTLIL::Const driver_mask;
a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name));
a_bit.wire = module->wire(remap_name(a_bit.wire->name));
y_bit.wire = module->wire(remap_name(y_bit.wire->name));
auto jt = bit2sinks.find(a_bit);
if (jt == bit2sinks.end())
@ -1614,7 +1614,7 @@ clone_lut:
y_bit,
driver_mask);
for (auto &bit : cell->connections_.at(ID::A)) {
bit.wire = module->wires_.at(remap_name(bit.wire->name));
bit.wire = module->wire(remap_name(bit.wire->name));
bit2sinks[bit].push_back(cell);
}
}

16
passes/techmap/clkbufmap.cc
View file

@ -145,16 +145,16 @@ struct ClkbufmapPass : public Pass {
auto wire = module->wire(port);
if (wire->get_bool_attribute(ID::clkbuf_driver))
for (int i = 0; i < GetSize(wire); i++)
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
if (wire->get_bool_attribute(ID::clkbuf_sink))
for (int i = 0; i < GetSize(wire); i++)
sink_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
sink_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
auto it = wire->attributes.find(ID::clkbuf_inv);
if (it != wire->attributes.end()) {
IdString in_name = RTLIL::escape_id(it->second.decode_string());
for (int i = 0; i < GetSize(wire); i++) {
inv_ports_out[make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i))] = make_pair(in_name, i);
inv_ports_in[make_pair(RTLIL::IdString(module->name), make_pair(in_name, i))] = make_pair(wire->name, i);
inv_ports_out[make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i))] = make_pair(in_name, i);
inv_ports_in[make_pair(RTLIL::IdString(module->name), make_pair(in_name, i))] = make_pair(RTLIL::IdString(wire->name), i);
}
}
}
@ -236,7 +236,7 @@ struct ClkbufmapPass : public Pass {
// some buffer higher up in the hierarchy.
if (wire->port_output)
for (int i = 0; i < GetSize(wire); i++)
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
continue;
}
@ -249,7 +249,7 @@ struct ClkbufmapPass : public Pass {
if (buf_wire_bits.count(mapped_wire_bit)) {
// Already buffered downstream. If this is an output, mark it.
if (wire->port_output)
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
} else if (!sink_wire_bits.count(mapped_wire_bit)) {
// Nothing to do.
} else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute(ID::top))) {
@ -288,7 +288,7 @@ struct ClkbufmapPass : public Pass {
// A clock input in a submodule -- mark it, let higher level
// worry about it.
if (wire->port_input)
sink_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
sink_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
}
}
if (!input_bits.empty()) {
@ -320,7 +320,7 @@ struct ClkbufmapPass : public Pass {
SigBit wire_bit(wire, i);
SigBit mapped_wire_bit = sigmap(wire_bit);
if (buffered_bits.count(mapped_wire_bit))
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
}
}

2
passes/techmap/dfflibmap.cc
View file

@ -512,7 +512,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
for (auto cell : cell_list)
{
auto cell_type = cell->type;
auto cell_name = cell->name;
RTLIL::IdString cell_name(cell->name);
auto cell_connections = cell->connections();
std::string src = cell->get_src_attribute();

10
passes/techmap/iopadmap.cc
View file

@ -217,7 +217,7 @@ struct IopadmapPass : public Pass {
// Collect explicitly-marked already-buffered SigBits.
for (auto wire : module->wires())
if (wire->get_bool_attribute(ID::iopad_external_pin) || ignore.count(make_pair(RTLIL::IdString(module->name), wire->name)))
if (wire->get_bool_attribute(ID::iopad_external_pin) || ignore.count(make_pair(RTLIL::IdString(module->name), RTLIL::IdString(wire->name))))
for (int i = 0; i < GetSize(wire); i++)
buf_bits.insert(sigmap(SigBit(wire, i)));
@ -233,7 +233,7 @@ struct IopadmapPass : public Pass {
if (wire->port_input || wire->port_output)
for (int i = 0; i < GetSize(wire); i++)
if (buf_bits.count(sigmap(SigBit(wire, i)))) {
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
log("Marking already mapped port: %s.%s[%d].\n", module, wire, i);
}
}
@ -293,7 +293,7 @@ struct IopadmapPass : public Pass {
SigBit wire_bit(wire, i);
Cell *tbuf_cell = nullptr;
if (buf_ports.count(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i))))
if (buf_ports.count(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i))))
continue;
if (tbuf_bits.count(wire_bit))
@ -370,7 +370,7 @@ struct IopadmapPass : public Pass {
if (!toutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(toutpad_portname_pad));
}
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
}
}
}
@ -384,7 +384,7 @@ struct IopadmapPass : public Pass {
pool<int> skip_bit_indices;
for (int i = 0; i < GetSize(wire); i++)
if (buf_ports.count(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i))))
if (buf_ports.count(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i))))
skip_bit_indices.insert(i);
if (GetSize(wire) == GetSize(skip_bit_indices))