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https://github.com/YosysHQ/yosys
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WIP
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parent
1a8a95b472
commit
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32 changed files with 1348 additions and 769 deletions
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@ -52,7 +52,7 @@ std::string getFileinfo(const RTLIL::AttrObject *design_entity, const RTLIL::Des
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// Get a port direction with respect to a specific module.
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FDirection getPortFDirection(IdString id, Module *module)
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{
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Wire *wire = module->wires_.at(id);
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Wire *wire = module->wire(id);
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FDirection direction = FD_NODIRECTION;
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if (wire && wire->port_id)
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{
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@ -41,9 +41,9 @@ void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const R
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Twine::Id id = design->obj_src_id(obj);
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f << stringf("%s" "attribute \\src ", indent);
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if (resolve_src) {
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dump_const(f, RTLIL::Const(design->src_twines.flatten(id)));
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dump_const(f, RTLIL::Const(design->twines.flatten(id)));
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} else {
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dump_const(f, RTLIL::Const(TwinePool::format_ref(id)));
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dump_const(f, RTLIL::Const(design->twines.format_ref(id)));
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}
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f << stringf("\n");
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}
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@ -56,10 +56,10 @@ void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const R
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void RTLIL_BACKEND::dump_twines(std::ostream &f, const RTLIL::Design *design)
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{
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if (!design || design->src_twines.size() == 0)
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if (!design || design->twines.size() == 0)
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return;
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f << stringf("twines\n");
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design->src_twines.for_each_live([&](Twine::Id id, const Twine &n) {
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design->twines.for_each_live([&](Twine::Id id, const Twine &n) {
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if (n.is_leaf()) {
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f << stringf(" leaf %u ", id);
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dump_const(f, RTLIL::Const(n.leaf()));
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@ -32,7 +32,7 @@ YOSYS_NAMESPACE_BEGIN
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namespace RTLIL_BACKEND {
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// If `design` is non-null AND `resolve_src` is true, the ID::src
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// attribute is expanded through design->src_twines so the emitted
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// attribute is expanded through design->twines so the emitted
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// value is the flat path:line.col string. Otherwise the stored value
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// is written verbatim — including any "@N" twine references, which
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// the matching `twines` header block emitted by dump_design lets the
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