3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-19 12:23:39 +00:00

add attributes for enumerated values in ilang

- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
This commit is contained in:
Jeff Wang 2020-02-03 01:12:24 -05:00 committed by Jeff Wang
parent 6320f2692b
commit d12ba42a74
5 changed files with 79 additions and 5 deletions

View file

@ -1222,6 +1222,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
}
else {
// must be global definition
(*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations
design->verilog_globals.push_back((*it)->clone());
}
}