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ecp5: Do not use specify in generate in cells_sim.v.

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Marcelina Kościelnicka 2022-02-21 16:30:42 +01:00
parent 1586000048
commit d0f4d0b153
1 changed files with 15 additions and 28 deletions
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43
techlibs/ecp5/cells_sim.v
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@ -355,37 +355,24 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
end end
endgenerate endgenerate
generate specify
// TODO $setup(DI, negedge CLK &&& CLKMUX == "INV", 0);
if (CLKMUX == "INV") $setup(CE, negedge CLK &&& CLKMUX == "INV", 0);
specify $setup(LSR, negedge CLK &&& CLKMUX == "INV", 0);
$setup(DI, negedge CLK, 0); $setup(DI, posedge CLK &&& CLKMUX != "INV", 0);
$setup(CE, negedge CLK, 0); $setup(CE, posedge CLK &&& CLKMUX != "INV", 0);
$setup(LSR, negedge CLK, 0); $setup(LSR, posedge CLK &&& CLKMUX != "INV", 0);
`ifndef YOSYS `ifndef YOSYS
if (SRMODE == "ASYNC" && muxlsr) (negedge CLK => (Q : srval)) = 0; if (SRMODE == "ASYNC" && muxlsr && CLKMUX == "INV") (negedge CLK => (Q : srval)) = 0;
if (SRMODE == "ASYNC" && muxlsr && CLKMUX != "INV") (posedge CLK => (Q : srval)) = 0;
`else `else
if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's // but for facilitating a bypass box, let's pretend it's
// a simple path // a simple path
`endif `endif
if (!muxlsr && muxce) (negedge CLK => (Q : DI)) = 0; if (!muxlsr && muxce && CLKMUX == "INV") (negedge CLK => (Q : DI)) = 0;
endspecify if (!muxlsr && muxce && CLKMUX != "INV") (posedge CLK => (Q : DI)) = 0;
else endspecify
specify
$setup(DI, posedge CLK, 0);
$setup(CE, posedge CLK, 0);
$setup(LSR, posedge CLK, 0);
`ifndef YOSYS
if (SRMODE == "ASYNC" && muxlsr) (posedge CLK => (Q : srval)) = 0;
`else
if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0;
endspecify
endgenerate
endmodule endmodule
// --------------------------------------- // ---------------------------------------