mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

ifndef __ICARUS__ -> ifdef YOSYS

Browse source
This commit is contained in:
Eddie Hung 2020-01-01 17:33:47 -08:00
parent db04161eca
commit d0d3ab8f67
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/xilinx/cells_sim.v
View file

@ -2160,13 +2160,13 @@ module DSP48E1 (
output reg [3:0] CARRYOUT,
output reg MULTSIGNOUT,
output OVERFLOW,
`ifndef __ICARUS__
`ifdef YOSYS
(* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *)
`endif
output reg signed [47:0] P,
output reg PATTERNBDETECT,
output reg PATTERNDETECT,
`ifndef __ICARUS__
`ifdef YOSYS
(* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *)
`endif
output [47:0] PCOUT,