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Merge pull request #5442 from rocallahan/verific-bus-ports

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Set `port_id` for Verific `PortBus` wires
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Miodrag Milanović 2025-11-03 10:04:07 +01:00 • committed by GitHub
commit d0a41d4f58
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tests/verific/port_bus_order.ys Normal file
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verific -sv <<EOT
module simple (
input [3:0] I2,
input [3:0] I1,
output [3:0] result
);
assign result = I2 & I1;
endmodule
EOT
verific -import simple
write_verilog verilog_port_bus_order.out
!grep -qF 'simple(I2, I1, result)' verilog_port_bus_order.out