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Move ConstEvalAig to aigerparse.cc

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This commit is contained in:
Eddie Hung 2019-06-13 16:28:11 -07:00
parent 75d89e56cf
commit d09d4e0706
2 changed files with 161 additions and 160 deletions
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157
kernel/consteval.h
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@ -390,163 +390,6 @@ struct ConstEval
}
};
struct ConstEvalAig
{
RTLIL::Module *module;
//SigMap assign_map;
SigMap values_map;
//SigPool stop_signals;
SigSet<RTLIL::Cell*> sig2driver;
//std::set<RTLIL::Cell*> busy;
//std::vector<SigMap> stack;
//RTLIL::State defaultval;
ConstEvalAig(RTLIL::Module *module /*, RTLIL::State defaultval = RTLIL::State::Sm*/) : module(module) /*, assign_map(module), defaultval(defaultval)*/
{
CellTypes ct;
ct.setup_internals();
ct.setup_stdcells();
for (auto &it : module->cells_) {
if (!ct.cell_known(it.second->type))
continue;
for (auto &it2 : it.second->connections())
if (ct.cell_output(it.second->type, it2.first))
sig2driver.insert(/*assign_map*/(it2.second), it.second);
}
}
void clear()
{
values_map.clear();
//stop_signals.clear();
}
//void push()
//{
// stack.push_back(values_map);
//}
//void pop()
//{
// values_map.swap(stack.back());
// stack.pop_back();
//}
void set(RTLIL::SigSpec sig, RTLIL::Const value)
{
//assign_map.apply(sig);
#ifndef NDEBUG
RTLIL::SigSpec current_val = values_map(sig);
for (int i = 0; i < GetSize(current_val); i++)
log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
#endif
values_map.add(sig, RTLIL::SigSpec(value));
}
//void stop(RTLIL::SigSpec sig)
//{
// assign_map.apply(sig);
// stop_signals.add(sig);
//}
bool eval(RTLIL::Cell *cell /*, RTLIL::SigSpec &undef*/)
{
RTLIL::SigSpec sig_y = values_map(/*assign_map*/(cell->getPort("\\Y")));
if (sig_y.is_fully_const())
return true;
RTLIL::SigSpec sig_a = cell->getPort("\\A");
if (sig_a.size() > 0 && !eval(sig_a /*, undef, cell*/))
return false;
RTLIL::Const eval_ret;
if (cell->type == "$_NOT_") {
if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1;
else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0;
}
else if (cell->type == "$_AND_") {
if (sig_a == RTLIL::S0) {
eval_ret = RTLIL::S0;
goto eval_end;
}
{
RTLIL::SigSpec sig_b = cell->getPort("\\B");
if (sig_b.size() > 0 && !eval(sig_b /*, undef, cell*/))
return false;
if (sig_b == RTLIL::S0) {
eval_ret = RTLIL::S0;
goto eval_end;
}
if (sig_a != RTLIL::State::S1 || sig_b != RTLIL::State::S1) {
eval_ret = RTLIL::State::Sx;
goto eval_end;
}
eval_ret = RTLIL::State::S1;
}
}
else log_abort();
eval_end:
set(sig_y, eval_ret);
return true;
}
bool eval(RTLIL::SigSpec &sig /*, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL*/)
{
//assign_map.apply(sig);
values_map.apply(sig);
if (sig.is_fully_const())
return true;
//if (stop_signals.check_any(sig)) {
// undef = stop_signals.extract(sig);
// return false;
//}
//if (busy_cell) {
// if (busy.count(busy_cell) > 0) {
// undef = sig;
// return false;
// }
// busy.insert(busy_cell);
//}
std::set<RTLIL::Cell*> driver_cells;
sig2driver.find(sig, driver_cells);
for (auto cell : driver_cells) {
if (!eval(cell /*, undef*/)) {
//if (busy_cell)
// busy.erase(busy_cell);
return false;
}
}
//if (busy_cell)
// busy.erase(busy_cell);
values_map.apply(sig);
if (sig.is_fully_const())
return true;
//for (auto &c : sig.chunks())
// if (c.wire != NULL)
// undef.append(c);
return false;
}
//bool eval(RTLIL::SigSpec &sig)
//{
// RTLIL::SigSpec undef;
// return eval(sig, undef);
//}
};
YOSYS_NAMESPACE_END
#endif