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Fixing selections

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This commit is contained in:
Krystine Sherwin 2025-03-14 14:08:14 +13:00
parent 091e9488fe
commit d09ae42951
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2 changed files with 5 additions and 5 deletions
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2
kernel/rtlil.cc
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@ -1185,7 +1185,7 @@ void RTLIL::Design::pop_selection()
std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const
{ {
bool include_partials = partials == RTLIL::SELECT_ALL; bool include_partials = partials == RTLIL::SELECT_ALL;
bool exclude_boxes = (partials & RTLIL::SB_UNBOXED_ONLY) == 0; bool exclude_boxes = (partials & RTLIL::SB_UNBOXED_ONLY) != 0;
bool ignore_wb = (partials & RTLIL::SB_INCL_WB) != 0; bool ignore_wb = (partials & RTLIL::SB_INCL_WB) != 0;
std::vector<RTLIL::Module*> result; std::vector<RTLIL::Module*> result;
result.reserve(modules_.size()); result.reserve(modules_.size());

8
passes/cmds/select.cc
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@ -1000,7 +1000,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel, bool whole_modules = false) static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel, bool whole_modules = false)
{ {
std::string desc = "Selection contains:\n"; std::string desc = "Selection contains:\n";
for (auto mod : design->selected_modules()) for (auto mod : design->all_selected_modules())
{ {
if (whole_modules && sel->selected_whole_module(mod->name)) if (whole_modules && sel->selected_whole_module(mod->name))
desc += stringf("%s\n", id2cstr(mod->name)); desc += stringf("%s\n", id2cstr(mod->name));
@ -1501,7 +1501,7 @@ struct SelectPass : public Pass {
design->push_selection(work_stack.back()); design->push_selection(work_stack.back());
RTLIL::Selection *sel = &design->selection(); RTLIL::Selection *sel = &design->selection();
sel->optimize(design); sel->optimize(design);
for (auto mod : design->selected_modules()) for (auto mod : design->all_selected_modules())
{ {
if (sel->selected_whole_module(mod->name) && list_mode) if (sel->selected_whole_module(mod->name) && list_mode)
log("%s\n", id2cstr(mod->name)); log("%s\n", id2cstr(mod->name));
@ -1578,7 +1578,7 @@ struct SelectPass : public Pass {
RTLIL::Selection *sel = &work_stack.back(); RTLIL::Selection *sel = &work_stack.back();
design->push_selection(*sel); design->push_selection(*sel);
sel->optimize(design); sel->optimize(design);
for (auto mod : design->selected_modules()) { for (auto mod : design->all_selected_modules()) {
module_count++; module_count++;
for ([[maybe_unused]] auto member_name : mod->selected_members()) for ([[maybe_unused]] auto member_name : mod->selected_members())
total_count++; total_count++;
@ -1777,7 +1777,7 @@ struct LsPass : public Pass {
{ {
std::vector<IdString> matches; std::vector<IdString> matches;
for (auto mod : design->selected_modules()) for (auto mod : design->all_selected_modules())
matches.push_back(mod->name); matches.push_back(mod->name);
if (!matches.empty()) { if (!matches.empty()) {