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Fix sf2 LUT interface

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-10-31 15:36:53 +01:00
parent cf79fd4376
commit d084fb4c3f
2 changed files with 12 additions and 12 deletions
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8
techlibs/sf2/cells_map.v
View file

@ -50,16 +50,16 @@ module \$lut (A, Y);
generate generate
if (WIDTH == 1) begin if (WIDTH == 1) begin
CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0])); CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
end else end else
if (WIDTH == 2) begin if (WIDTH == 2) begin
CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1])); CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
end else end else
if (WIDTH == 3) begin if (WIDTH == 3) begin
CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]), .C(A[2])); CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
end else end else
if (WIDTH == 4) begin if (WIDTH == 4) begin
CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
end else begin end else begin
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
end end

16
techlibs/sf2/cells_sim.v
View file

@ -37,39 +37,39 @@ module SLE (
endmodule endmodule
module CFG1 ( module CFG1 (
output O, output Y,
input A input A
); );
parameter [1:0] INIT = 2'h0; parameter [1:0] INIT = 2'h0;
assign O = INIT >> A; assign Y = INIT >> A;
endmodule endmodule
module CFG2 ( module CFG2 (
output O, output Y,
input A, input A,
input B input B
); );
parameter [3:0] INIT = 4'h0; parameter [3:0] INIT = 4'h0;
assign O = INIT >> {B, A}; assign Y = INIT >> {B, A};
endmodule endmodule
module CFG3 ( module CFG3 (
output O, output Y,
input A, input A,
input B, input B,
input C input C
); );
parameter [7:0] INIT = 8'h0; parameter [7:0] INIT = 8'h0;
assign O = INIT >> {C, B, A}; assign Y = INIT >> {C, B, A};
endmodule endmodule
module CFG4 ( module CFG4 (
output O, output Y,
input A, input A,
input B, input B,
input C, input C,
input D input D
); );
parameter [15:0] INIT = 16'h0; parameter [15:0] INIT = 16'h0;
assign O = INIT >> {D, C, B, A}; assign Y = INIT >> {D, C, B, A};
endmodule endmodule