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Fix sf2 LUT interface

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-10-31 15:36:53 +01:00
parent cf79fd4376
commit d084fb4c3f
2 changed files with 12 additions and 12 deletions
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16
techlibs/sf2/cells_sim.v
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@ -37,39 +37,39 @@ module SLE (
endmodule
module CFG1 (
output O,
output Y,
input A
);
parameter [1:0] INIT = 2'h0;
assign O = INIT >> A;
assign Y = INIT >> A;
endmodule
module CFG2 (
output O,
output Y,
input A,
input B
);
parameter [3:0] INIT = 4'h0;
assign O = INIT >> {B, A};
assign Y = INIT >> {B, A};
endmodule
module CFG3 (
output O,
output Y,
input A,
input B,
input C
);
parameter [7:0] INIT = 8'h0;
assign O = INIT >> {C, B, A};
assign Y = INIT >> {C, B, A};
endmodule
module CFG4 (
output O,
output Y,
input A,
input B,
input C,
input D
);
parameter [15:0] INIT = 16'h0;
assign O = INIT >> {D, C, B, A};
assign Y = INIT >> {D, C, B, A};
endmodule