mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-01 12:07:51 +00:00
Code Activity

Progress on xsthammer

Browse source
This commit is contained in:
Clifford Wolf 2013-06-10 12:37:05 +02:00
parent af83ed168e
commit d07b32ade5
5 changed files with 268 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

69
tests/xsthammer/xl_cells.v Normal file
View file

@ -0,0 +1,69 @@
module GND(G);
output G = 0;
endmodule
module INV(O, I);
input I;
output O = !I;
endmodule
module LUT2(O, I0, I1);
parameter INIT = 0;
input I0, I1;
wire [3:0] lutdata = INIT;
wire [1:0] idx = { I1, I0 };
output O = lutdata[idx];
endmodule
module LUT3(O, I0, I1, I2);
parameter INIT = 0;
input I0, I1, I2;
wire [7:0] lutdata = INIT;
wire [2:0] idx = { I2, I1, I0 };
output O = lutdata[idx];
endmodule
module LUT4(O, I0, I1, I2, I3);
parameter INIT = 0;
input I0, I1, I2, I3;
wire [15:0] lutdata = INIT;
wire [3:0] idx = { I3, I2, I1, I0 };
output O = lutdata[idx];
endmodule
module LUT5(O, I0, I1, I2, I3, I4);
parameter INIT = 0;
input I0, I1, I2, I3, I4;
wire [31:0] lutdata = INIT;
wire [4:0] idx = { I4, I3, I2, I1, I0 };
output O = lutdata[idx];
endmodule
module LUT6(O, I0, I1, I2, I3, I4, I5);
parameter INIT = 0;
input I0, I1, I2, I3, I4, I5;
wire [63:0] lutdata = INIT;
wire [5:0] idx = { I5, I4, I3, I2, I1, I0 };
output O = lutdata[idx];
endmodule
module MUXCY(O, CI, DI, S);
input CI, DI, S;
output O = S ? CI : DI;
endmodule
module MUXF7(O, I0, I1, S);
input I0, I1, S;
output O = S ? I1 : I0;
endmodule
module VCC(P);
output P = 1;
endmodule
module XORCY(O, CI, LI);
input CI, LI;
output O = CI ^ LI;
endmodule