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Clean up passes/sat/qbfsat.cc.
This commit is contained in:
Alberto Gonzalez
parent
437afa1f0c
commit
d07ac2612b
1 changed files with 101 additions and 86 deletions
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@ -54,8 +54,9 @@ struct QbfSolveOptions {
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std::string specialize_soln_file;
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std::string write_soln_soln_file;
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std::string dump_final_smt2_file;
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size_t argidx;
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QbfSolveOptions() : timeout(false), specialize(false), specialize_from_file(false), write_solution(false),
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nocleanup(false), dump_final_smt2(false), timeout_sec(-1) {};
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nocleanup(false), dump_final_smt2(false), timeout_sec(-1), argidx(0) {};
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};
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void recover_solution(QbfSolutionType &sol) {
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@ -118,6 +119,21 @@ void specialize(RTLIL::Module *module, const QbfSolutionType &ret) {
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}
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}
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void allconstify_inputs(RTLIL::Module *module, const std::set<std::string> &input_wires) {
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for(auto &n : input_wires) {
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RTLIL::Wire *input = module->wire(n);
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log_assert(input != nullptr);
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RTLIL::Cell *allconst = module->addCell("$allconst$" + n, "$allconst");
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allconst->setParam(ID(WIDTH), input->width);
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allconst->setPort(ID::Y, input);
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allconst->set_src_attribute(input->get_src_attribute());
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input->port_input = false;
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log("Replaced input %s with $allconst cell.\n", n.c_str());
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}
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module->fixup_ports();
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}
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QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
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QbfSolutionType ret;
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std::string yosys_smtbmc_exe = proc_self_dirname() + "yosys-smtbmc";
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@ -193,6 +209,86 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
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return ret;
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}
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std::set<std::string> validate_design_and_get_inputs(RTLIL::Module *module) {
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bool found_input = false;
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bool found_hole = false;
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bool found_1bit_output = false;
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std::set<std::string> input_wires;
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for (auto wire : module->wires()) {
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if (wire->port_input) {
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found_input = true;
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input_wires.insert(wire->name.str());
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}
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if (wire->port_output && wire->width == 1)
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found_1bit_output = true;
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}
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for (auto cell : module->cells()) {
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if (cell->type == "$allconst")
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found_input = true;
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if (cell->type == "$anyconst")
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found_hole = true;
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if (cell->type.in("$assert", "$assume"))
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found_1bit_output = true;
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}
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if (!found_input)
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log_cmd_error("Can't perform QBF-SAT on a miter with no inputs!\n");
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if (!found_hole)
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log_cmd_error("Did not find any existentially-quantified variables. Use 'sat' instead.\n");
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if (!found_1bit_output)
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log_cmd_error("Did not find any single-bit outputs, assert()s, or assume()s. Is this a miter circuit?\n");
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return input_wires;
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}
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QbfSolveOptions parse_args(const std::vector<std::string> &args) {
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QbfSolveOptions opt;
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for (opt.argidx = 1; opt.argidx < args.size(); opt.argidx++) {
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if (args[opt.argidx] == "-timeout") {
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opt.timeout = true;
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if (args.size() <= opt.argidx + 1)
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log_cmd_error("timeout not specified.\n");
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else
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opt.timeout_sec = atol(args[++opt.argidx].c_str());
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continue;
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}
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else if (args[opt.argidx] == "-nocleanup") {
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opt.nocleanup = true;
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continue;
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}
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else if (args[opt.argidx] == "-specialize") {
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opt.specialize = true;
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continue;
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}
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else if (args[opt.argidx] == "-dump-final-smt2") {
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opt.dump_final_smt2 = true;
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if (args.size() <= opt.argidx + 1)
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log_cmd_error("smt2 file not specified.\n");
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else
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opt.dump_final_smt2_file = args[++opt.argidx];
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continue;
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}
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else if (args[opt.argidx] == "-specialize-from-file") {
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opt.specialize_from_file = true;
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if (args.size() <= opt.argidx + 1)
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log_cmd_error("solution file not specified.\n");
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else
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opt.specialize_soln_file = args[++opt.argidx];
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continue;
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}
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else if (args[opt.argidx] == "-write-solution") {
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opt.write_solution = true;
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if (args.size() <= opt.argidx + 1)
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log_cmd_error("solution file not specified.\n");
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else
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opt.write_soln_soln_file = args[++opt.argidx];
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continue;
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}
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break;
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}
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return opt;
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}
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void print_proof_failed()
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{
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@ -260,54 +356,10 @@ struct QbfSatPass : public Pass {
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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QbfSolveOptions opt;
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log_header(design, "Executing QBF-SAT pass (solving QBF-SAT problems in the circuit).\n");
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QbfSolveOptions opt = parse_args(args);
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extra_args(args, opt.argidx, design);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-timeout") {
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opt.timeout = true;
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if (args.size() <= argidx + 1)
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log_cmd_error("timeout not specified.\n");
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else
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opt.timeout_sec = atol(args[++argidx].c_str());
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continue;
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}
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else if (args[argidx] == "-nocleanup") {
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opt.nocleanup = true;
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continue;
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}
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else if (args[argidx] == "-specialize") {
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opt.specialize = true;
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continue;
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}
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else if (args[argidx] == "-dump-final-smt2") {
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opt.dump_final_smt2 = true;
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if (args.size() <= argidx + 1)
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log_cmd_error("smt2 file not specified.\n");
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else
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opt.dump_final_smt2_file = args[++argidx];
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continue;
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}
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else if (args[argidx] == "-specialize-from-file") {
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opt.specialize_from_file = true;
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if (args.size() <= argidx + 1)
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log_cmd_error("solution file not specified.\n");
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else
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opt.specialize_soln_file = args[++argidx];
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continue;
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}
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else if (args[argidx] == "-write-solution") {
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opt.write_solution = true;
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if (args.size() <= argidx + 1)
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log_cmd_error("solution file not specified.\n");
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else
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opt.write_soln_soln_file = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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RTLIL::Module *module = NULL;
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for (auto mod : design->selected_modules()) {
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@ -318,50 +370,13 @@ struct QbfSatPass : public Pass {
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if (module == NULL)
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log_cmd_error("Can't perform QBF-SAT on an empty selection!\n");
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bool found_input = false;
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bool found_hole = false;
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bool found_1bit_output = false;
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std::set<std::string> input_wires;
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for (auto wire : module->wires()) {
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if (wire->port_input) {
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found_input = true;
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input_wires.insert(wire->name.str());
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}
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if (wire->port_output && wire->width == 1)
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found_1bit_output = true;
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}
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for (auto cell : module->cells()) {
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if (cell->type == "$allconst")
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found_input = true;
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if (cell->type == "$anyconst")
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found_hole = true;
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if (cell->type.in("$assert", "$assume"))
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found_1bit_output = true;
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}
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if (!found_input)
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log_cmd_error("Can't perform QBF-SAT on a miter with no inputs!\n");
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if (!found_hole)
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log_cmd_error("Did not find any existentially-quantified variables. Use 'sat' instead.\n");
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if (!found_1bit_output)
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log_cmd_error("Did not find any single-bit outputs, assert()s, or assume()s. Is this a miter circuit?\n");
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//Save the design to restore after modiyfing the current module.
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std::string module_name = module->name.str();
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Pass::call(design, "design -save _qbfsat_tmp");
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//Replace input wires with wires assigned $allconst cells.
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for(auto &n : input_wires) {
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RTLIL::Wire *input = module->wire(n);
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log_assert(input != nullptr);
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RTLIL::Cell *allconst = module->addCell("$allconst$" + n, "$allconst");
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allconst->setParam(ID(WIDTH), input->width);
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allconst->setPort(ID::Y, input);
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allconst->set_src_attribute(input->get_src_attribute());
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input->port_input = false;
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log("Replaced input %s with $allconst cell.\n", n.c_str());
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}
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module->fixup_ports();
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std::set<std::string> input_wires = validate_design_and_get_inputs(module);
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allconstify_inputs(module, input_wires);
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QbfSolutionType ret = qbf_solve(module, opt);
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Pass::call(design, "design -load _qbfsat_tmp");
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