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https://github.com/YosysHQ/yosys
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hashlib: redo interface for flexibility
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7a362f1f74
commit
d071489ab1
35 changed files with 542 additions and 386 deletions
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@ -95,7 +95,7 @@ namespace RTLIL
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} destruct_guard;
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static std::vector<char*> global_id_storage_;
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static dict<char*, int, hash_cstr_ops> global_id_index_;
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static dict<char*, int> global_id_index_;
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#ifndef YOSYS_NO_IDS_REFCNT
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static std::vector<int> global_refcount_storage_;
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static std::vector<int> global_free_idx_list_;
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@ -360,8 +360,8 @@ namespace RTLIL
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*this = IdString();
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}
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unsigned int hash() const {
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return index_;
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Hasher hash_acc(Hasher h) const {
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return hash_ops<int>::hash_acc(index_, h);
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}
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// The following is a helper key_compare class. Instead of for example std::set<Cell*>
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@ -796,11 +796,10 @@ public:
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bv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());
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}
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inline unsigned int hash() const {
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unsigned int h = mkhash_init;
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for (State b : *this)
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h = mkhash(h, b);
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inline Hasher hash_acc(Hasher h) const {
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// TODO hash size
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for (auto b : *this)
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h.acc(b);
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return h;
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}
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};
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@ -890,7 +889,7 @@ struct RTLIL::SigBit
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bool operator <(const RTLIL::SigBit &other) const;
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bool operator ==(const RTLIL::SigBit &other) const;
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bool operator !=(const RTLIL::SigBit &other) const;
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unsigned int hash() const;
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Hasher hash_acc(Hasher h) const;
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};
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struct RTLIL::SigSpecIterator
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@ -931,7 +930,7 @@ struct RTLIL::SigSpec
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{
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private:
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int width_;
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unsigned long hash_;
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Hasher::hash_t hash_;
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std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0
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std::vector<RTLIL::SigBit> bits_; // LSB at index 0
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@ -972,9 +971,10 @@ public:
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SigSpec(const std::set<RTLIL::SigBit> &bits);
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explicit SigSpec(bool bit);
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[[deprecated]]
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size_t get_hash() const {
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if (!hash_) hash();
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return hash_;
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log_assert(false && "deprecated");
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return 0;
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}
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inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }
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@ -1083,7 +1083,7 @@ public:
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operator std::vector<RTLIL::SigBit>() const { return bits(); }
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const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
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unsigned int hash() const { if (!hash_) updhash(); return hash_; };
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Hasher hash_acc(Hasher h) const { if (!hash_) updhash(); h.acc(hash_); return h; }
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#ifndef NDEBUG
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void check(Module *mod = nullptr) const;
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@ -1124,8 +1124,8 @@ struct RTLIL::Selection
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struct RTLIL::Monitor
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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Hasher::hash_t hashidx_;
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Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
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Monitor() {
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static unsigned int hashidx_count = 123456789;
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@ -1147,8 +1147,8 @@ struct define_map_t;
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struct RTLIL::Design
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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Hasher::hash_t hashidx_;
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Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
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pool<RTLIL::Monitor*> monitors;
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dict<std::string, std::string> scratchpad;
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@ -1252,8 +1252,8 @@ struct RTLIL::Design
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struct RTLIL::Module : public RTLIL::AttrObject
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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Hasher::hash_t hashidx_;
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Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
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protected:
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void add(RTLIL::Wire *wire);
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@ -1607,8 +1607,8 @@ void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
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struct RTLIL::Wire : public RTLIL::AttrObject
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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Hasher::hash_t hashidx_;
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Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
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protected:
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// use module->addWire() and module->remove() to create or destroy wires
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@ -1646,8 +1646,8 @@ inline int GetSize(RTLIL::Wire *wire) {
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struct RTLIL::Memory : public RTLIL::AttrObject
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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Hasher::hash_t hashidx_;
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Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
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Memory();
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@ -1661,8 +1661,8 @@ struct RTLIL::Memory : public RTLIL::AttrObject
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struct RTLIL::Cell : public RTLIL::AttrObject
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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Hasher::hash_t hashidx_;
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Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
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protected:
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// use module->addCell() and module->remove() to create or destroy cells
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@ -1771,8 +1771,8 @@ struct RTLIL::SyncRule
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struct RTLIL::Process : public RTLIL::AttrObject
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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Hasher::hash_t hashidx_;
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Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
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protected:
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// use module->addProcess() and module->remove() to create or destroy processes
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@ -1816,10 +1816,14 @@ inline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {
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return (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));
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}
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inline unsigned int RTLIL::SigBit::hash() const {
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if (wire)
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return mkhash_add(wire->name.hash(), offset);
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return data;
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inline Hasher RTLIL::SigBit::hash_acc(Hasher h) const {
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if (wire) {
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h = wire->name.hash_acc(h);
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h.acc(offset);
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return h;
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}
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h.acc(data);
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return h;
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}
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inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {
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