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hashlib: redo interface for flexibility

This commit is contained in:
Emil J. Tywoniak 2024-10-01 15:12:03 +02:00
parent 7a362f1f74
commit d071489ab1
35 changed files with 542 additions and 386 deletions

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@ -95,7 +95,7 @@ namespace RTLIL
} destruct_guard;
static std::vector<char*> global_id_storage_;
static dict<char*, int, hash_cstr_ops> global_id_index_;
static dict<char*, int> global_id_index_;
#ifndef YOSYS_NO_IDS_REFCNT
static std::vector<int> global_refcount_storage_;
static std::vector<int> global_free_idx_list_;
@ -360,8 +360,8 @@ namespace RTLIL
*this = IdString();
}
unsigned int hash() const {
return index_;
Hasher hash_acc(Hasher h) const {
return hash_ops<int>::hash_acc(index_, h);
}
// The following is a helper key_compare class. Instead of for example std::set<Cell*>
@ -796,11 +796,10 @@ public:
bv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());
}
inline unsigned int hash() const {
unsigned int h = mkhash_init;
for (State b : *this)
h = mkhash(h, b);
inline Hasher hash_acc(Hasher h) const {
// TODO hash size
for (auto b : *this)
h.acc(b);
return h;
}
};
@ -890,7 +889,7 @@ struct RTLIL::SigBit
bool operator <(const RTLIL::SigBit &other) const;
bool operator ==(const RTLIL::SigBit &other) const;
bool operator !=(const RTLIL::SigBit &other) const;
unsigned int hash() const;
Hasher hash_acc(Hasher h) const;
};
struct RTLIL::SigSpecIterator
@ -931,7 +930,7 @@ struct RTLIL::SigSpec
{
private:
int width_;
unsigned long hash_;
Hasher::hash_t hash_;
std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0
std::vector<RTLIL::SigBit> bits_; // LSB at index 0
@ -972,9 +971,10 @@ public:
SigSpec(const std::set<RTLIL::SigBit> &bits);
explicit SigSpec(bool bit);
[[deprecated]]
size_t get_hash() const {
if (!hash_) hash();
return hash_;
log_assert(false && "deprecated");
return 0;
}
inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }
@ -1083,7 +1083,7 @@ public:
operator std::vector<RTLIL::SigBit>() const { return bits(); }
const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
unsigned int hash() const { if (!hash_) updhash(); return hash_; };
Hasher hash_acc(Hasher h) const { if (!hash_) updhash(); h.acc(hash_); return h; }
#ifndef NDEBUG
void check(Module *mod = nullptr) const;
@ -1124,8 +1124,8 @@ struct RTLIL::Selection
struct RTLIL::Monitor
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
Hasher::hash_t hashidx_;
Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
Monitor() {
static unsigned int hashidx_count = 123456789;
@ -1147,8 +1147,8 @@ struct define_map_t;
struct RTLIL::Design
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
Hasher::hash_t hashidx_;
Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
pool<RTLIL::Monitor*> monitors;
dict<std::string, std::string> scratchpad;
@ -1252,8 +1252,8 @@ struct RTLIL::Design
struct RTLIL::Module : public RTLIL::AttrObject
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
Hasher::hash_t hashidx_;
Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
protected:
void add(RTLIL::Wire *wire);
@ -1607,8 +1607,8 @@ void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
struct RTLIL::Wire : public RTLIL::AttrObject
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
Hasher::hash_t hashidx_;
Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
protected:
// use module->addWire() and module->remove() to create or destroy wires
@ -1646,8 +1646,8 @@ inline int GetSize(RTLIL::Wire *wire) {
struct RTLIL::Memory : public RTLIL::AttrObject
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
Hasher::hash_t hashidx_;
Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
Memory();
@ -1661,8 +1661,8 @@ struct RTLIL::Memory : public RTLIL::AttrObject
struct RTLIL::Cell : public RTLIL::AttrObject
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
Hasher::hash_t hashidx_;
Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
protected:
// use module->addCell() and module->remove() to create or destroy cells
@ -1771,8 +1771,8 @@ struct RTLIL::SyncRule
struct RTLIL::Process : public RTLIL::AttrObject
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
Hasher::hash_t hashidx_;
Hasher hash_acc(Hasher h) const { h.acc(hashidx_); return h; }
protected:
// use module->addProcess() and module->remove() to create or destroy processes
@ -1816,10 +1816,14 @@ inline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {
return (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));
}
inline unsigned int RTLIL::SigBit::hash() const {
if (wire)
return mkhash_add(wire->name.hash(), offset);
return data;
inline Hasher RTLIL::SigBit::hash_acc(Hasher h) const {
if (wire) {
h = wire->name.hash_acc(h);
h.acc(offset);
return h;
}
h.acc(data);
return h;
}
inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {