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hashlib: redo interface for flexibility
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parent
7a362f1f74
commit
d071489ab1
35 changed files with 542 additions and 386 deletions
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@ -48,8 +48,11 @@ struct ModIndex : public RTLIL::Monitor
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return cell == other.cell && port == other.port && offset == other.offset;
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}
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unsigned int hash() const {
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return mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);
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Hasher hash_acc(Hasher h) const {
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h.acc(cell->name);
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h.acc(port);
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h.acc(offset);
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return h;
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}
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};
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@ -57,6 +60,8 @@ struct ModIndex : public RTLIL::Monitor
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{
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bool is_input, is_output;
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pool<PortInfo> ports;
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// SigBitInfo() : SigBitInfo{} {}
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// SigBitInfo& operator=(const SigBitInfo&) = default;
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SigBitInfo() : is_input(false), is_output(false) { }
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@ -304,6 +309,8 @@ struct ModWalker
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RTLIL::Cell *cell;
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RTLIL::IdString port;
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int offset;
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PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}
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// PortBit& operator=(const PortBit&) = default;
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bool operator<(const PortBit &other) const {
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if (cell != other.cell)
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@ -317,8 +324,11 @@ struct ModWalker
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return cell == other.cell && port == other.port && offset == other.offset;
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}
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unsigned int hash() const {
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return mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);
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Hasher hash_acc(Hasher h) const {
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h.acc(cell->name);
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h.acc(port);
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h.acc(offset);
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return h;
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}
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};
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@ -355,7 +365,7 @@ struct ModWalker
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{
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for (int i = 0; i < int(bits.size()); i++)
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if (bits[i].wire != NULL) {
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PortBit pbit = { cell, port, i };
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PortBit pbit {cell, port, i};
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if (is_output) {
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signal_drivers[bits[i]].insert(pbit);
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cell_outputs[cell].insert(bits[i]);
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