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Merge pull request #1981 from YosysHQ/claire/fix1837

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Clear current_scope when done with RTLIL generation
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Claire Wolf 2020-05-01 14:58:41 +02:00 • committed by GitHub
commit d047ca8b11
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4
frontends/ast/ast.cc
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@ -946,6 +946,7 @@ RTLIL::Const AstNode::realAsConst(int width)
// create a new AstModule from an AST_MODULE AST node // create a new AstModule from an AST_MODULE AST node
static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false) static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false)
{ {
log_assert(current_scope.empty());
log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE); log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
if (defer) if (defer)
@ -1117,6 +1118,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
} }
ignoreThisSignalsInInitial = RTLIL::SigSpec(); ignoreThisSignalsInInitial = RTLIL::SigSpec();
current_scope.clear();
} }
else { else {
for (auto &attr : ast->attributes) { for (auto &attr : ast->attributes) {
@ -1229,11 +1231,13 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
// process enum/other declarations // process enum/other declarations
(*it)->simplify(true, false, false, 1, -1, false, false); (*it)->simplify(true, false, false, 1, -1, false, false);
design->verilog_packages.push_back((*it)->clone()); design->verilog_packages.push_back((*it)->clone());
current_scope.clear();
} }
else { else {
// must be global definition // must be global definition
(*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations (*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations
design->verilog_globals.push_back((*it)->clone()); design->verilog_globals.push_back((*it)->clone());
current_scope.clear();
} }
} }
} }