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ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT

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Eddie Hung 2019-07-13 01:11:00 -07:00
parent 7dc15bdd2d
commit d032198fac
1 changed files with 7 additions and 9 deletions
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16
techlibs/ice40/ice40_opt.cc
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@ -114,19 +114,17 @@ static void run_ice40_opts(Module *module)
optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO")[0], replacement_output); module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true); module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n", log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output)); log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "\\SB_LUT4"; cell->type = "$lut";
cell->setPort("\\I0", RTLIL::S0); cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
cell->setPort("\\I1", inbit[0]); cell->setPort("\\Y", cell->getPort("\\O"));
cell->setPort("\\I2", inbit[1]);
cell->setPort("\\I3", inbit[2]);
cell->unsetPort("\\A");
cell->unsetPort("\\B"); cell->unsetPort("\\B");
cell->unsetPort("\\CI"); cell->unsetPort("\\CI");
cell->unsetPort("\\CO"); cell->unsetPort("\\CO");
cell->setParam("\\LUT_INIT", RTLIL::Const::from_string("0110100110010110")); cell->unsetPort("\\O");
sb_lut_cells.push_back(cell); cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
cell->setParam("\\WIDTH", 4);
} }
continue; continue;
} }