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https://github.com/YosysHQ/yosys
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Major refactoring of equiv_struct
This commit is contained in:
Clifford Wolf
parent
207736b4ee
commit
d014ba2d0e
2 changed files with 176 additions and 99 deletions
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@ -162,6 +162,11 @@ struct hash_obj_ops {
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}
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};
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template<typename T>
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inline unsigned int mkhash(const T &v) {
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return hash_ops<T>().hash(v);
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}
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inline int hashtable_size(int min_size)
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{
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static std::vector<int> zero_and_some_primes = {
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@ -28,64 +28,67 @@ struct EquivStructWorker
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Module *module;
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SigMap sigmap;
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SigMap equiv_bits;
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bool mode_fwd;
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bool mode_icells;
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int merge_count;
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dict<IdString, pool<IdString>> cells_by_type;
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void handle_cell_pair(Cell *cell_a, Cell *cell_b)
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struct merge_key_t
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{
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if (cell_a->parameters != cell_b->parameters)
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return;
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IdString type;
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vector<pair<IdString, Const>> parameters;
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vector<pair<IdString, int>> port_sizes;
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vector<tuple<IdString, int, SigBit>> connections;
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bool merge_this_cells = false;
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bool found_diff_inputs = false;
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vector<SigSpec> inputs_a, inputs_b;
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bool operator==(const merge_key_t &other) const {
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return type == other.type && connections == other.connections &&
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parameters == other.parameters && port_sizes == other.port_sizes;
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}
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unsigned int hash() const {
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unsigned int h = mkhash_init;
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h = mkhash(h, mkhash(type));
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h = mkhash(h, mkhash(parameters));
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h = mkhash(h, mkhash(connections));
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return h;
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}
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};
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dict<merge_key_t, pool<IdString>> merge_cache;
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pool<merge_key_t> fwd_merge_cache, bwd_merge_cache;
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void merge_cell_pair(Cell *cell_a, Cell *cell_b)
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{
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SigMap merged_map;
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merge_count++;
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SigSpec inputs_a, inputs_b;
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vector<string> input_names;
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for (auto &port_a : cell_a->connections())
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{
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SigSpec bits_a = equiv_bits(port_a.second);
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SigSpec bits_b = equiv_bits(cell_b->getPort(port_a.first));
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SigSpec bits_a = sigmap(port_a.second);
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SigSpec bits_b = sigmap(cell_b->getPort(port_a.first));
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if (GetSize(bits_a) != GetSize(bits_b))
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return;
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log_assert(GetSize(bits_a) == GetSize(bits_b));
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if (cell_a->output(port_a.first)) {
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for (int i = 0; i < GetSize(bits_a); i++)
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if (bits_a[i] == bits_b[i])
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merge_this_cells = true;
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} else {
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SigSpec diff_bits_a, diff_bits_b;
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if (!cell_a->output(port_a.first))
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for (int i = 0; i < GetSize(bits_a); i++)
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if (bits_a[i] != bits_b[i]) {
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diff_bits_a.append(bits_a[i]);
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diff_bits_b.append(bits_b[i]);
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}
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if (!diff_bits_a.empty()) {
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inputs_a.push_back(diff_bits_a);
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inputs_b.push_back(diff_bits_b);
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found_diff_inputs = true;
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inputs_a.append(bits_a[i]);
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inputs_b.append(bits_b[i]);
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input_names.push_back(GetSize(bits_a) == 1 ? port_a.first.str() :
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stringf("%s[%d]", log_id(port_a.first), i));
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}
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}
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}
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if (!found_diff_inputs)
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merge_this_cells = true;
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if (merge_this_cells)
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{
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SigMap merged_map;
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log(" Merging cells %s and %s.\n", log_id(cell_a), log_id(cell_b));
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merge_count++;
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for (int i = 0; i < GetSize(inputs_a); i++) {
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SigSpec &sig_a = inputs_a[i], &sig_b = inputs_b[i];
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SigSpec sig_y = module->addWire(NEW_ID, GetSize(sig_a));
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log(" A: %s, B: %s, Y: %s\n", log_signal(sig_a), log_signal(sig_b), log_signal(sig_y));
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module->addEquiv(NEW_ID, sig_a, sig_b, sig_y);
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merged_map.add(sig_a, sig_y);
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merged_map.add(sig_b, sig_y);
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SigBit bit_a = inputs_a[i], bit_b = inputs_b[i];
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SigBit bit_y = module->addWire(NEW_ID);
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log(" New $equiv for input %s: A: %s, B: %s, Y: %s\n",
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input_names[i].c_str(), log_signal(bit_a), log_signal(bit_b), log_signal(bit_y));
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module->addEquiv(NEW_ID, bit_a, bit_b, bit_y);
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merged_map.add(bit_a, bit_y);
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merged_map.add(bit_b, bit_y);
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}
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std::vector<IdString> outport_names, inport_names;
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@ -97,14 +100,12 @@ struct EquivStructWorker
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inport_names.push_back(port_a.first);
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for (auto &pn : inport_names)
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cell_a->setPort(pn, merged_map(equiv_bits(cell_a->getPort(pn))));
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cell_a->setPort(pn, merged_map(sigmap(cell_a->getPort(pn))));
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for (auto &pn : outport_names) {
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SigSpec sig_a = cell_a->getPort(pn);
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SigSpec sig_b = cell_b->getPort(pn);
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module->connect(sig_b, sig_a);
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sigmap.add(sig_b, sig_a);
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equiv_bits.add(sig_b, sig_a);
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}
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auto merged_attr = cell_b->get_strpool_attribute("\\equiv_merged");
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@ -112,14 +113,15 @@ struct EquivStructWorker
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cell_a->add_strpool_attribute("\\equiv_merged", merged_attr);
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module->remove(cell_b);
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}
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}
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EquivStructWorker(Module *module, bool mode_icells) :
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module(module), sigmap(module), equiv_bits(module), mode_icells(mode_icells), merge_count(0)
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EquivStructWorker(Module *module, bool mode_fwd, bool mode_icells) :
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module(module), sigmap(module), equiv_bits(module),
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mode_fwd(mode_fwd), mode_icells(mode_icells), merge_count(0)
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{
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log(" Starting new iteration.\n");
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pool<SigBit> equiv_inputs;
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pool<IdString> cells;
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for (auto cell : module->selected_cells())
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if (cell->type == "$equiv") {
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@ -128,15 +130,14 @@ struct EquivStructWorker
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equiv_bits.add(sig_b, sig_a);
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equiv_inputs.insert(sig_a);
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equiv_inputs.insert(sig_b);
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cells_by_type[cell->type].insert(cell->name);
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} else
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if (module->design->selected(module, cell)) {
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cells.insert(cell->name);
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} else {
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if (mode_icells || module->design->module(cell->type))
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cells_by_type[cell->type].insert(cell->name);
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cells.insert(cell->name);
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}
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for (auto cell_name : cells_by_type["$equiv"]) {
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Cell *cell = module->cell(cell_name);
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for (auto cell : module->selected_cells())
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if (cell->type == "$equiv") {
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SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
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SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
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SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit());
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@ -150,23 +151,83 @@ struct EquivStructWorker
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if (merge_count > 0)
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return;
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for (auto &it : cells_by_type)
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for (auto cell_name : cells)
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{
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if (it.second.size() <= 1)
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merge_key_t key;
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vector<tuple<IdString, int, SigBit>> fwd_connections;
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Cell *cell = module->cell(cell_name);
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key.type = cell->type;
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for (auto &it : cell->parameters)
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key.parameters.push_back(it);
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std::sort(key.parameters.begin(), key.parameters.end());
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for (auto &it : cell->connections())
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key.port_sizes.push_back(make_pair(it.first, GetSize(it.second)));
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std::sort(key.port_sizes.begin(), key.port_sizes.end());
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for (auto &conn : cell->connections())
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{
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SigSpec sig = equiv_bits(conn.second);
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if (cell->input(conn.first))
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for (int i = 0; i < GetSize(sig); i++)
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fwd_connections.push_back(make_tuple(conn.first, i, sig[i]));
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if (cell->output(conn.first))
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for (int i = 0; i < GetSize(sig); i++) {
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key.connections.clear();
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key.connections.push_back(make_tuple(conn.first, i, sig[i]));
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if (merge_cache.count(key))
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bwd_merge_cache.insert(key);
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merge_cache[key].insert(cell_name);
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}
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}
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std::sort(fwd_connections.begin(), fwd_connections.end());
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key.connections.swap(fwd_connections);
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if (merge_cache.count(key))
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fwd_merge_cache.insert(key);
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merge_cache[key].insert(cell_name);
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}
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for (int phase = 0; phase < 2; phase++)
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{
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auto &queue = phase ? bwd_merge_cache : fwd_merge_cache;
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for (auto &key : queue)
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{
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Cell *gold_cell = nullptr;
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pool<Cell*> cells;
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for (auto cell_name : merge_cache[key]) {
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Cell *c = module->cell(cell_name);
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if (c != nullptr) {
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string n = cell_name.str();
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if (gold_cell == nullptr || (GetSize(n) > 5 && n.substr(GetSize(n)-5) == "_gold"))
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gold_cell = c;
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cells.insert(c);
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}
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}
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if (GetSize(cells) < 2)
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continue;
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log(" Merging %s cells..\n", log_id(it.first));
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for (auto gate_cell : cells)
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if (gate_cell != gold_cell) {
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log(" %s merging cells %s and %s.\n", phase ? "Bwd" : "Fwd", log_id(gold_cell), log_id(gate_cell));
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merge_cell_pair(gold_cell, gate_cell);
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}
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}
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// FIXME: O(n^2)
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for (auto cell_name_a : it.second)
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for (auto cell_name_b : it.second)
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if (cell_name_a < cell_name_b) {
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Cell *cell_a = module->cell(cell_name_a);
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Cell *cell_b = module->cell(cell_name_b);
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if (cell_a && cell_b)
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handle_cell_pair(cell_a, cell_b);
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}
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if (merge_count > 0)
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return;
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}
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log(" Nothing to merge.\n");
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}
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};
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@ -184,6 +245,12 @@ struct EquivStructPass : public Pass {
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log("for example when analyzing circuits with cells with commutative inputs. This\n");
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log("command will also de-duplicate gates.\n");
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log("\n");
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log(" -fwd\n");
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log(" by default this command performans forward sweeps until nothing can\n");
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log(" be merged by forwards sweeps, the backward sweeps until forward\n");
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log(" sweeps are effective again. with this option set only forward sweeps\n");
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log(" are performed.\n");
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log("\n");
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log(" -icells\n");
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log(" by default, the internal RTL and gate cell types are ignored. add\n");
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log(" this option to also process those cell types with this command.\n");
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@ -192,11 +259,16 @@ struct EquivStructPass : public Pass {
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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bool mode_icells = false;
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bool mode_fwd = false;
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log_header("Executing EQUIV_STRUCT pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-fwd") {
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mode_fwd = true;
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continue;
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}
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if (args[argidx] == "-icells") {
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mode_icells = true;
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continue;
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@ -206,9 +278,9 @@ struct EquivStructPass : public Pass {
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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log("Running equiv_struct on module %s:", log_id(module));
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log("Running equiv_struct on module %s:\n", log_id(module));
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while (1) {
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EquivStructWorker worker(module, mode_icells);
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EquivStructWorker worker(module, mode_fwd, mode_icells);
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if (worker.merge_count == 0)
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break;
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}
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