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verilog: fix signedness when removing unreachable cases

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This commit is contained in:
Jannis Harder 2022-05-24 14:32:14 +02:00 • committed by Zachary Snow
parent c525b5f919
commit cffec1f95f
3 changed files with 39 additions and 0 deletions
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1
frontends/ast/simplify.cc
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@ -1531,6 +1531,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
detectSignWidth(width_hint, sign_hint);
while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { }
if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) {
children[0]->is_signed = sign_hint;
RTLIL::Const case_expr = children[0]->bitsAsConst(width_hint, sign_hint);
std::vector<AstNode*> new_children;
new_children.push_back(children[0]);