mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-02 08:10:46 +00:00
Code Activity

verilog: fix signedness when removing unreachable cases

Browse source
This commit is contained in:
Jannis Harder 2022-05-24 14:32:14 +02:00 • committed by Zachary Snow
parent c525b5f919
commit cffec1f95f
3 changed files with 39 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

5
CHANGELOG
View file

@ -5,6 +5,11 @@ List of major changes and improvements between releases
Yosys 0.17 .. Yosys 0.17-dev
--------------------------
* Verilog
- Fixed an issue where simplifying case statements by removing unreachable
cases could result in the wrong signedness being used for comparison with
the remaining cases
Yosys 0.16 .. Yosys 0.17
--------------------------
* New commands and options