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Patch: route staged cell names through per-Patch dict
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2 changed files with 6 additions and 2 deletions
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@ -26,6 +26,7 @@ public:
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SigMap* map;
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vector<std::unique_ptr<Wire>> wires_ = {};
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vector<std::unique_ptr<Cell>> cells_ = {};
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dict<RTLIL::Cell*, RTLIL::IdString> staged_cell_names_;
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void connect(const RTLIL::SigSig &conn);
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void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
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