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Patch: route staged cell names through per-Patch dict

This commit is contained in:
Emil J. Tywoniak 2026-06-05 16:45:50 +02:00
parent 0f31d3089e
commit cfd7edc608
2 changed files with 6 additions and 2 deletions

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@ -26,6 +26,7 @@ public:
SigMap* map;
vector<std::unique_ptr<Wire>> wires_ = {};
vector<std::unique_ptr<Cell>> cells_ = {};
dict<RTLIL::Cell*, RTLIL::IdString> staged_cell_names_;
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);