mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-01 20:17:55 +00:00
Code Activity

Import tests from #1628

Browse source
This commit is contained in:
Eddie Hung 2020-01-27 13:56:16 -08:00
parent ce6a690d27
commit cfb0366a18
3 changed files with 104 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

30
tests/arch/ice40/ice40_opt.ys
View file

@ -86,3 +86,33 @@ select -assert-count 1 t:SB_LUT4
select -assert-count 1 t:SB_CARRY
select -assert-count 1 t:SB_CARRY a:keep %i
select -assert-count 1 t:SB_CARRY c:carry %i
design -reset
read_verilog -icells <<EOT
module top(input I3, I2, I1, I0, output O, O2);
SB_LUT4 #(
.LUT_INIT(8'b 1001_0110)
) u0 (
.I0(I0),
.I1(I1),
.I2(I2),
.I3(),
.O(O)
);
wire CO;
\$__ICE40_CARRY_WRAPPER #(
.LUT(~8'b 1001_0110),
.I3_IS_CI(1'b0)
) u1 (
.A(1'b0),
.B(1'b0),
.CI(1'b0),
.I0(),
.I3(),
.CO(CO),
.O(O2)
);
endmodule
EOT
ice40_opt