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Basic SmartFusion2 and IGLOO2 synthesis support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
db676957a0
commit
cf79fd4376
5 changed files with 377 additions and 0 deletions
7
techlibs/sf2/Makefile.inc
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7
techlibs/sf2/Makefile.inc
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OBJS += techlibs/sf2/synth_sf2.o
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$(eval $(call add_share_file,share/sf2,techlibs/sf2/arith_map.v))
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$(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_map.v))
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$(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_sim.v))
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21
techlibs/sf2/arith_map.v
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21
techlibs/sf2/arith_map.v
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// nothing here yet
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68
techlibs/sf2/cells_map.v
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68
techlibs/sf2/cells_map.v
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// module \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
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module \$_DFF_P_ (input D, C, output Q);
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SLE _TECHMAP_REPLACE_ (
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.D(D),
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.CLK(C),
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.EN(1'b1),
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.ALn(1'b1),
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.ADn(1'b1),
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.SLn(1'b1),
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.SD(1'b0),
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.LAT(1'b0),
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.Q(Q)
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);
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endmodule
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// module \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
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// module \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
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//
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// module \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
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// module \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
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//
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// module \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
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// module \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
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// module \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
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// module \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
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//
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// module \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
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// module \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
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// module \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
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// module \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
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//
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// module \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
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// module \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
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// module \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
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// module \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
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//
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// module \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
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// module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
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// module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
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// module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
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`ifndef NO_LUT
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]));
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end else
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if (WIDTH == 2) begin
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CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]));
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end else
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if (WIDTH == 3) begin
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CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]), .C(A[2]));
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end else
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if (WIDTH == 4) begin
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CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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`endif
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75
techlibs/sf2/cells_sim.v
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75
techlibs/sf2/cells_sim.v
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module SLE (
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output Q,
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input ADn,
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input ALn,
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input CLK,
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input D,
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input LAT,
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input SD,
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input EN,
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input SLn
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);
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reg q_latch, q_ff;
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always @(posedge CLK, negedge ALn) begin
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if (!ALn) begin
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q_ff <= !ADn;
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end else if (EN) begin
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if (!SLn)
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q_ff <= SD;
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else
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q_ff <= D;
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end
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end
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always @* begin
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if (!ALn) begin
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q_latch <= !ADn;
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end else if (CLK && EN) begin
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if (!SLn)
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q_ff <= SD;
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else
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q_ff <= D;
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end
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end
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assign Q = LAT ? q_latch : q_ff;
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endmodule
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module CFG1 (
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output O,
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input A
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);
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parameter [1:0] INIT = 2'h0;
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assign O = INIT >> A;
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endmodule
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module CFG2 (
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output O,
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input A,
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input B
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);
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parameter [3:0] INIT = 4'h0;
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assign O = INIT >> {B, A};
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endmodule
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module CFG3 (
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output O,
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input A,
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input B,
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input C
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);
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parameter [7:0] INIT = 8'h0;
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assign O = INIT >> {C, B, A};
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endmodule
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module CFG4 (
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output O,
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input A,
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input B,
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input C,
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input D
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);
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parameter [15:0] INIT = 16'h0;
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assign O = INIT >> {D, C, B, A};
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endmodule
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206
techlibs/sf2/synth_sf2.cc
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206
techlibs/sf2/synth_sf2.cc
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthSf2Pass : public ScriptPass
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{
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SynthSf2Pass() : ScriptPass("synth_sf2", "synthesis for SmartFusion2 and IGLOO2 FPGAs") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_sf2 [options]\n");
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log("\n");
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log("This command runs synthesis for SmartFusion2 and IGLOO2 FPGAs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified EDIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, edif_file, json_file;
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bool flatten, retime;
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void clear_flags() YS_OVERRIDE
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{
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top_opt = "-auto-top";
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edif_file = "";
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json_file = "";
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flatten = true;
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retime = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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break;
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|
}
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|
extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This comannd only operates on fully selected designs!\n");
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log_header(design, "Executing SYNTH_SF2 pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() YS_OVERRIDE
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib +/sf2/cells_sim.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (flatten && check_label("flatten", "(unless -noflatten)"))
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{
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run("proc");
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run("flatten");
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|
run("tribuf -logic");
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run("deminout");
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|
}
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|
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if (check_label("coarse"))
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{
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run("synth -run coarse");
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}
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if (check_label("fine"))
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{
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run("opt -fast -mux_undef -undriven -fine");
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run("memory_map");
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run("opt -undriven -fine");
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run("techmap -map +/techmap.v -map +/sf2/arith_map.v");
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||||||
|
if (retime || help_mode)
|
||||||
|
run("abc -dff", "(only if -retime)");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (check_label("map_ffs"))
|
||||||
|
{
|
||||||
|
run("dffsr2dff");
|
||||||
|
run("techmap -D NO_LUT -map +/sf2/cells_map.v");
|
||||||
|
run("opt_expr -mux_undef");
|
||||||
|
run("simplemap");
|
||||||
|
// run("sf2_ffinit");
|
||||||
|
// run("sf2_ffssr");
|
||||||
|
// run("sf2_opt -full");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (check_label("map_luts"))
|
||||||
|
{
|
||||||
|
run("abc -lut 4");
|
||||||
|
run("clean");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (check_label("map_cells"))
|
||||||
|
{
|
||||||
|
run("techmap -map +/sf2/cells_map.v");
|
||||||
|
run("clean");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (check_label("check"))
|
||||||
|
{
|
||||||
|
run("hierarchy -check");
|
||||||
|
run("stat");
|
||||||
|
run("check -noinit");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (check_label("edif"))
|
||||||
|
{
|
||||||
|
if (!edif_file.empty() || help_mode)
|
||||||
|
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
|
||||||
|
}
|
||||||
|
|
||||||
|
if (check_label("json"))
|
||||||
|
{
|
||||||
|
if (!json_file.empty() || help_mode)
|
||||||
|
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} SynthSf2Pass;
|
||||||
|
|
||||||
|
PRIVATE_NAMESPACE_END
|
||||||
Loading…
Add table
Add a link
Reference in a new issue