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sta: more graceful when maxbit is not an endpoint, will still print path

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This commit is contained in:
Eddie Hung 2020-03-31 15:18:03 -07:00
parent 72d73fe4d0
commit cf6b60f79c
2 changed files with 32 additions and 17 deletions
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34
passes/cmds/sta.cc
View file

@ -171,10 +171,10 @@ struct StaWorker
data[dst_bit].backtrack = b; data[dst_bit].backtrack = b;
data[dst_bit].src_port = std::get<2>(d); data[dst_bit].src_port = std::get<2>(d);
}
auto it = endpoints.find(dst_bit); auto it = endpoints.find(dst_bit);
if (it != endpoints.end()) { if (it != endpoints.end())
new_arrival += it->second.required; new_arrival += it->second.required;
if (new_arrival > maxarrival) { if (new_arrival > maxarrival) {
maxarrival = new_arrival; maxarrival = new_arrival;
maxbit = dst_bit; maxbit = dst_bit;
@ -185,26 +185,26 @@ struct StaWorker
log("Latest arrival time in '%s' is %d:\n", log_id(module), maxarrival); log("Latest arrival time in '%s' is %d:\n", log_id(module), maxarrival);
auto b = maxbit; auto b = maxbit;
const auto &e = endpoints.at(maxbit); auto it = endpoints.find(maxbit);
if (e.sink) if (it != endpoints.end() && it->second.sink)
log(" %6d %s (%s.%s)\n", maxarrival, log_id(e.sink), log_id(e.sink->type), log_id(e.port)); log(" %6d %s (%s.%s)\n", maxarrival, log_id(it->second.sink), log_id(it->second.sink->type), log_id(it->second.port));
else if (b.wire->port_output) else {
log(" %6d (%s)\n", maxarrival, "<primary output>"); log(" %6d (%s)\n", maxarrival, b.wire->port_output ? "<primary output>" : "<unknown>");
else log_warning("Critical-path does not terminate in a recognised endpoint.\n");
log_abort(); }
auto it = data.find(b); auto jt = data.find(b);
while (it != data.end()) { while (jt != data.end()) {
int arrival = b.wire->get_intvec_attribute(ID(sta_arrival))[b.offset]; int arrival = b.wire->get_intvec_attribute(ID(sta_arrival))[b.offset];
if (it->second.driver) { if (jt->second.driver) {
log(" %s\n", log_signal(b)); log(" %s\n", log_signal(b));
log(" %6d %s (%s.%s->%s)\n", arrival, log_id(it->second.driver), log_id(it->second.driver->type), log_id(it->second.src_port), log_id(it->second.dst_port)); log(" %6d %s (%s.%s->%s)\n", arrival, log_id(jt->second.driver), log_id(jt->second.driver->type), log_id(jt->second.src_port), log_id(jt->second.dst_port));
} }
else if (b.wire->port_input) else if (b.wire->port_input)
log(" %6d %s (%s)\n", arrival, log_signal(b), "<primary input>"); log(" %6d %s (%s)\n", arrival, log_signal(b), "<primary input>");
else else
log_abort(); log_abort();
b = it->second.backtrack; b = jt->second.backtrack;
it = data.find(b); jt = data.find(b);
} }
std::map<int, unsigned> arrival_histogram; std::map<int, unsigned> arrival_histogram;

15
tests/various/sta.ys Normal file
View file

@ -0,0 +1,15 @@
read_verilog -specify <<EOT
module buffer(input i, output o);
specify
(i => o) = 10;
endspecify
endmodule
module top(input i);
wire w;
buffer b(.i(i), .o(w));
endmodule
EOT
logger -expect warning "Critical-path does not terminate in a recognised endpoint\." 1
sta