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Add abc9_ops -reintegrate; moved out from now abc9_exe
This commit is contained in:
Eddie Hung
parent
46ed507b93
commit
cf3a13746d
4 changed files with 315 additions and 361 deletions
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@ -26,6 +26,13 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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int map_autoidx;
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inline std::string remap_name(RTLIL::IdString abc9_name)
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{
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return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
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}
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void break_scc(RTLIL::Module *module)
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{
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// For every unique SCC found, (arbitrarily) find the first
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@ -416,6 +423,276 @@ void prep_holes(RTLIL::Module *module, bool dff)
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}
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}
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void reintegrate(RTLIL::Module *module)
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{
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auto design = module->design;
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log_assert(design);
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map_autoidx = autoidx++;
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RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
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if (mapped_mod == NULL)
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log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
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for (auto w : mapped_mod->wires())
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module->addWire(remap_name(w->name), GetSize(w));
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for (auto it = module->cells_.begin(); it != module->cells_.end(); )
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if (it->second->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
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it = module->cells_.erase(it);
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else
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++it;
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
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dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
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std::map<IdString, int> cell_stats;
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for (auto mapped_cell : mapped_mod->cells())
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{
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toposort.node(mapped_cell->name);
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RTLIL::Cell *cell = nullptr;
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if (mapped_cell->type == ID($_NOT_)) {
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RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
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RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
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bit_users[a_bit].insert(mapped_cell->name);
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bit_drivers[y_bit].insert(mapped_cell->name);
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if (!a_bit.wire) {
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mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
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RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
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log_assert(wire);
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module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
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}
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else {
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RTLIL::Cell* driver_lut = nullptr;
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// ABC can return NOT gates that drive POs
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if (!a_bit.wire->port_input) {
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// If it's not a NOT gate that that comes from a PI directly,
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// find the driver LUT and clone that to guarantee that we won't
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// increase the max logic depth
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// (TODO: Optimise by not cloning unless will increase depth)
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RTLIL::IdString driver_name;
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if (GetSize(a_bit.wire) == 1)
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driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
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else
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driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
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driver_lut = mapped_mod->cell(driver_name);
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}
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if (!driver_lut) {
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// If a driver couldn't be found (could be from PI or box CI)
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// then implement using a LUT
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cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
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RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
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RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
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RTLIL::Const::from_string("01"));
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bit2sinks[cell->getPort(ID::A)].push_back(cell);
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cell_stats[ID($lut)]++;
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}
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else
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not2drivers[mapped_cell] = driver_lut;
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}
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continue;
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}
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cell_stats[mapped_cell->type]++;
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RTLIL::Cell *existing_cell = nullptr;
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if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
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if (mapped_cell->type == ID($lut) &&
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GetSize(mapped_cell->getPort(ID::A)) == 1 &&
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mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
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SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
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SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
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module->connect(my_y, my_a);
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log_abort();
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continue;
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}
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cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
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}
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else {
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existing_cell = module->cell(mapped_cell->name);
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log_assert(existing_cell);
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cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
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}
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RTLIL::Module* box_module = design->module(mapped_cell->type);
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auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop");
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for (auto &mapped_conn : mapped_cell->connections()) {
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RTLIL::SigSpec newsig;
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for (auto c : mapped_conn.second.chunks()) {
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if (c.width == 0)
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continue;
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//log_assert(c.width == 1);
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if (c.wire)
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c.wire = module->wires_.at(remap_name(c.wire->name));
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newsig.append(c);
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}
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if (existing_cell) {
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auto it = existing_cell->connections_.find(mapped_conn.first);
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if (it == existing_cell->connections_.end())
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continue;
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log_assert(GetSize(newsig) >= GetSize(it->second));
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newsig = newsig.extract(0, GetSize(it->second));
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}
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cell->setPort(mapped_conn.first, newsig);
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if (abc9_flop)
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continue;
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if (cell->input(mapped_conn.first)) {
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for (auto i : newsig)
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bit2sinks[i].push_back(cell);
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for (auto i : mapped_conn.second)
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bit_users[i].insert(mapped_cell->name);
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}
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if (cell->output(mapped_conn.first))
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for (auto i : mapped_conn.second)
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bit_drivers[i].insert(mapped_cell->name);
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}
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if (existing_cell) {
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cell->parameters = existing_cell->parameters;
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cell->attributes = existing_cell->attributes;
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if (cell->attributes.erase("\\abc9_box_seq")) {
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module->swap_names(cell, existing_cell);
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module->remove(existing_cell);
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}
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}
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else {
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cell->parameters = mapped_cell->parameters;
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cell->attributes = mapped_cell->attributes;
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}
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}
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// Copy connections (and rename) from mapped_mod to module
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for (auto conn : mapped_mod->connections()) {
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if (!conn.first.is_fully_const()) {
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auto chunks = conn.first.chunks();
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for (auto &c : chunks)
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c.wire = module->wires_.at(remap_name(c.wire->name));
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conn.first = std::move(chunks);
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}
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if (!conn.second.is_fully_const()) {
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auto chunks = conn.second.chunks();
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for (auto &c : chunks)
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if (c.wire)
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c.wire = module->wires_.at(remap_name(c.wire->name));
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conn.second = std::move(chunks);
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}
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module->connect(conn);
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}
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for (auto &it : cell_stats)
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log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
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int in_wires = 0, out_wires = 0;
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// Stitch in mapped_mod's inputs/outputs into module
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for (auto port : mapped_mod->ports) {
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RTLIL::Wire *w = mapped_mod->wire(port);
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RTLIL::Wire *wire = module->wire(port);
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log_assert(wire);
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RTLIL::Wire *remap_wire = module->wire(remap_name(port));
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RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
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log_assert(GetSize(signal) >= GetSize(remap_wire));
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RTLIL::SigSig conn;
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if (w->port_output) {
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conn.first = signal;
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conn.second = remap_wire;
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out_wires++;
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module->connect(conn);
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}
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else if (w->port_input) {
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conn.first = remap_wire;
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conn.second = signal;
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in_wires++;
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module->connect(conn);
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}
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}
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
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log_assert(no_loops);
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for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
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RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
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log_assert(not_cell);
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if (not_cell->type != ID($_NOT_))
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continue;
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auto it = not2drivers.find(not_cell);
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if (it == not2drivers.end())
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continue;
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RTLIL::Cell *driver_lut = it->second;
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RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
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RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
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RTLIL::Const driver_mask;
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a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
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y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name));
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auto jt = bit2sinks.find(a_bit);
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if (jt == bit2sinks.end())
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goto clone_lut;
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for (auto sink_cell : jt->second)
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if (sink_cell->type != ID($lut))
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goto clone_lut;
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// Push downstream LUTs past inverter
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for (auto sink_cell : jt->second) {
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SigSpec A = sink_cell->getPort(ID::A);
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RTLIL::Const mask = sink_cell->getParam(ID(LUT));
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int index = 0;
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for (; index < GetSize(A); index++)
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if (A[index] == a_bit)
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break;
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log_assert(index < GetSize(A));
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int i = 0;
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while (i < GetSize(mask)) {
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for (int j = 0; j < (1 << index); j++)
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std::swap(mask[i+j], mask[i+j+(1 << index)]);
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i += 1 << (index+1);
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}
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A[index] = y_bit;
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sink_cell->setPort(ID::A, A);
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sink_cell->setParam(ID(LUT), mask);
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}
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// Since we have rewritten all sinks (which we know
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// to be only LUTs) to be after the inverter, we can
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// go ahead and clone the LUT with the expectation
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// that the original driving LUT will become dangling
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// and get cleaned away
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clone_lut:
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driver_mask = driver_lut->getParam(ID(LUT));
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for (auto &b : driver_mask.bits) {
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if (b == RTLIL::State::S0) b = RTLIL::State::S1;
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else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
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}
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auto cell = module->addLut(NEW_ID,
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driver_lut->getPort(ID::A),
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y_bit,
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driver_mask);
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for (auto &bit : cell->connections_.at(ID::A)) {
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bit.wire = module->wires_.at(remap_name(bit.wire->name));
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bit2sinks[bit].push_back(cell);
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}
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}
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//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
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log("ABC RESULTS: input signals: %8d\n", in_wires);
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log("ABC RESULTS: output signals: %8d\n", out_wires);
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design->remove(mapped_mod);
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}
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struct Abc9OpsPass : public Pass {
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Abc9OpsPass() : Pass("abc9_ops", "helper functions for ABC9") { }
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void help() YS_OVERRIDE
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@ -433,6 +710,7 @@ struct Abc9OpsPass : public Pass {
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bool unbreak_scc_mode = false;
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bool prep_dff_mode = false;
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bool prep_holes_mode = false;
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bool reintegrate_mode = false;
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bool dff_mode = false;
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size_t argidx;
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@ -454,6 +732,10 @@ struct Abc9OpsPass : public Pass {
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prep_holes_mode = true;
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continue;
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}
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if (arg == "-reintegrate") {
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reintegrate_mode = true;
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continue;
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}
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if (arg == "-dff") {
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dff_mode = true;
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continue;
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@ -463,8 +745,6 @@ struct Abc9OpsPass : public Pass {
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extra_args(args, argidx, design);
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for (auto mod : design->selected_modules()) {
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if (mod->get_blackbox_attribute())
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continue;
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if (mod->get_bool_attribute("\\abc9_holes"))
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continue;
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@ -481,6 +761,8 @@ struct Abc9OpsPass : public Pass {
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prep_dff(mod);
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if (prep_holes_mode)
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prep_holes(mod, dff_mode);
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if (reintegrate_mode)
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reintegrate(mod);
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}
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}
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} Abc9OpsPass;
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