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Re-added clean after techmap in synth_xilinx

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-22 09:03:11 +02:00
parent cbd9b8a3f3
commit cf1ba46fa0
1 changed files with 2 additions and 0 deletions
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2
techlibs/xilinx/synth_xilinx.cc
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@ -124,6 +124,7 @@ struct SynthXilinxPass : public Pass
log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n");
log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
log(" clean\n");
log("\n"); log("\n");
log(" check:\n"); log(" check:\n");
log(" hierarchy -check\n"); log(" hierarchy -check\n");
@ -280,6 +281,7 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
Pass::call(design, "clean");
} }
if (check_label(active, run_from, run_to, "check")) if (check_label(active, run_from, run_to, "check"))