Merge branch 'YosysHQ:main' into main

CHANGELOG

@@ -2,9 +2,14 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.49 .. Yosys 0.50-dev
+Yosys 0.50 .. Yosys 0.51-dev
 --------------------------
 
+Yosys 0.49 .. Yosys 0.50
+--------------------------
+ * Various
+    - "write_verilog" emits "$check" cell names as labels.
+
 Yosys 0.48 .. Yosys 0.49
 --------------------------
  * Various

Makefile

@@ -171,7 +171,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.49+29
+YOSYS_VER := 0.50+1
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -187,7 +187,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 427b5a2.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline b5170e1.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 

docs/source/conf.py

@@ -6,7 +6,7 @@ import os
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2025 YosysHQ GmbH'
-yosys_ver = "0.49"
+yosys_ver = "0.50"
 
 # select HTML theme
 html_theme = 'furo-ys'

passes/memory/memory_libmap.cc

@@ -2258,6 +2258,8 @@ struct MemoryLibMapPass : public Pass {
 					log("using FF mapping for memory %s.%s\n", log_id(module->name), log_id(mem.memid));
 				} else {
 					map.emit(map.cfgs[idx]);
+					// Rebuild indices after modifying module
+					worker = MapWorker(module);
 				}
 			}
 		}