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patch: infer leaves for gc
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parent
1cd0d37511
commit
cef8186c4a
4 changed files with 18 additions and 8 deletions
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@ -19,12 +19,13 @@ protected:
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Cell* commit_cell(std::unique_ptr<Cell> cell);
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Wire* commit_wire(std::unique_ptr<Wire> wire);
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pool<Wire*> leaves = {};
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public:
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Module* mod;
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SigMap* map;
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vector<std::unique_ptr<Wire>> wires_ = {};
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vector<std::unique_ptr<Cell>> cells_ = {};
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pool<Wire*> leaves = {};
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void connect(const RTLIL::SigSig &conn);
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void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
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@ -39,6 +40,8 @@ public:
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RTLIL::Cell* addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
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RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src);
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Patch(Module* mod, SigMap* map = nullptr) : mod(mod), map(map) {}
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};
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YOSYS_NAMESPACE_END
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