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patch: infer leaves for gc

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This commit is contained in:
Emil J. Tywoniak 2026-05-28 12:56:13 +02:00
parent 1cd0d37511
commit cef8186c4a
4 changed files with 18 additions and 8 deletions
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12
kernel/unstable/patch.cc
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@ -156,6 +156,18 @@ void Patch::patch(Cell* old_cell, IdString old_port, SigSpec new_sig) {
if (map)
map->add(old_sig, new_sig);
// Inefficient
for (auto& cell : cells_) {
for (auto& [port_name, sig] : cell->connections()) {
auto dir = cell->port_dir(port_name);
if (dir == PD_INPUT || dir == PD_INOUT) {
for (auto bit : sig)
if (bit.is_wire() && bit.wire->module)
leaves.insert(bit.wire);
}
}
}
for (auto& cell: cells_) {
cell->set_src_attribute(src_str);
cell->fixup_parameters();

5
kernel/unstable/patch.h
View file

@ -19,12 +19,13 @@ protected:
Cell* commit_cell(std::unique_ptr<Cell> cell);
Wire* commit_wire(std::unique_ptr<Wire> wire);
pool<Wire*> leaves = {};
public:
Module* mod;
SigMap* map;
vector<std::unique_ptr<Wire>> wires_ = {};
vector<std::unique_ptr<Cell>> cells_ = {};
pool<Wire*> leaves = {};
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
@ -39,6 +40,8 @@ public:
RTLIL::Cell* addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src);
Patch(Module* mod, SigMap* map = nullptr) : mod(mod), map(map) {}
};
YOSYS_NAMESPACE_END