mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-12-18 10:18:35 +00:00
Code Activity

aiger2: formatting

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-12-01 19:40:17 +01:00
parent 34fa8a4ff7
commit cebb80250c
1 changed files with 9 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

14
backends/aiger2/aiger.cc
View file

@ -24,6 +24,7 @@
#include "kernel/register.h" #include "kernel/register.h"
#include "kernel/celltypes.h" #include "kernel/celltypes.h"
#include "kernel/rtlil.h"
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
@ -845,11 +846,14 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
return false; return false;
int max = 1; int max = 1;
for (auto wire : mod->wires()) for (auto wire : mod->wires()) {
if (wire->port_input && !wire->port_output) if (wire->port_input && !wire->port_output) {
for (int i = 0; i < wire->width; i++) { SigSpec port = driver->getPort(wire->name);
int ilevel = visit(cursor, driver->getPort(wire->name)[i]); for (int i = 0; i < wire->width; i++) {
max = std::max(max, ilevel + 1); int ilevel = visit(cursor, port[i]);
max = std::max(max, ilevel + 1);
}
}
} }
lits[idx] = max; lits[idx] = max;