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Replace std::sets using custom comparators with pool.

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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
This commit is contained in:
Alberto Gonzalez 2020-04-20 22:55:11 +00:00
parent dabeb1e8a1
commit ce62d0751a
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GPG key ID: 8395A8BA109708B2
1 changed files with 4 additions and 4 deletions
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8
passes/techmap/techmap.cc
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@ -65,7 +65,7 @@ struct TechmapWorker
dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers; dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache; dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
dict<RTLIL::Module*, bool> techmap_do_cache; dict<RTLIL::Module*, bool> techmap_do_cache;
std::set<RTLIL::Module*, IdString::compare_ptr_by_name<RTLIL::Module>> module_queue; pool<RTLIL::Module*> module_queue;
dict<Module*, SigMap> sigmaps; dict<Module*, SigMap> sigmaps;
pool<IdString> flatten_do_list; pool<IdString> flatten_do_list;
@ -465,7 +465,7 @@ struct TechmapWorker
} }
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells, bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells,
const dict<IdString, std::set<IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion) const dict<IdString, pool<IdString>> &celltypeMap, bool in_recursion)
{ {
std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
@ -1305,7 +1305,7 @@ struct TechmapPass : public Pass {
log_header(design, "Continuing TECHMAP pass.\n"); log_header(design, "Continuing TECHMAP pass.\n");
dict<IdString, std::set<IdString, RTLIL::sort_by_id_str>> celltypeMap; dict<IdString, pool<IdString>> celltypeMap;
for (auto module : map->modules()) { for (auto module : map->modules()) {
if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) { if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str()); char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
@ -1386,7 +1386,7 @@ struct FlattenPass : public Pass {
extra_args(args, argidx, design); extra_args(args, argidx, design);
dict<IdString, std::set<IdString, RTLIL::sort_by_id_str>> celltypeMap; dict<IdString, pool<IdString>> celltypeMap;
for (auto module : design->modules()) for (auto module : design->modules())
celltypeMap[module->name].insert(module->name); celltypeMap[module->name].insert(module->name);