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synth_xilinx: Initial Spartan 6 block RAM inference support.
This commit is contained in:
Marcin Kościelnicki
parent
9112850800
commit
ce250b341c
9 changed files with 598 additions and 8 deletions
255
techlibs/xilinx/xc6s_brams_map.v
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255
techlibs/xilinx/xc6s_brams_map.v
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module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [9215:0] INIT = 9216'bx;
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input CLK2;
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input CLK3;
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input [7:0] A1ADDR;
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output [35:0] A1DATA;
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input A1EN;
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input [7:0] B1ADDR;
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input [35:0] B1DATA;
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input [3:0] B1EN;
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wire [12:0] A1ADDR_13 = {A1ADDR, 5'b0};
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wire [12:0] B1ADDR_13 = {B1ADDR, 5'b0};
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wire [3:0] DIP, DOP;
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wire [31:0] DI, DO;
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assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB8BWER #(
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.RAM_MODE("SDP"),
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.DATA_WIDTH_A(36),
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.DATA_WIDTH_B(36),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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`include "brams_init_9.vh"
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) _TECHMAP_REPLACE_ (
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.DOBDO(DO[31:16]),
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.DOADO(DO[15:0]),
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.DOPBDOP(DOP[3:2]),
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.DOPADOP(DOP[1:0]),
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.DIBDI(DI[31:16]),
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.DIADI(DI[15:0]),
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.DIPBDIP(DIP[3:2]),
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.DIPADIP(DIP[1:0]),
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.WEBWEU(B1EN[3:2]),
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.WEAWEL(B1EN[1:0]),
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.ADDRAWRADDR(B1ADDR_13),
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.CLKAWRCLK(CLK3 ^ !CLKPOL3),
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.ENAWREN(|1),
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.REGCEA(|0),
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.RSTA(|0),
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.ADDRBRDADDR(A1ADDR_13),
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.CLKBRDCLK(CLK2 ^ !CLKPOL2),
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.ENBRDEN(A1EN),
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.REGCEBREGCE(|1),
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.RSTB(|0)
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB16BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 9;
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parameter CFG_DBITS = 36;
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parameter CFG_ENABLE_B = 4;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [18431:0] INIT = 18432'bx;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input [CFG_ENABLE_B-1:0] B1EN;
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wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
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wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
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wire [3:0] B1EN_4 = {4{B1EN}};
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wire [3:0] DIP, DOP;
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wire [31:0] DI, DO;
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wire [31:0] DOB;
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wire [3:0] DOPB;
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assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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generate if (CFG_DBITS > 8) begin
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RAMB16BWER #(
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.DATA_WIDTH_A(CFG_DBITS),
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.DATA_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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`include "brams_init_18.vh"
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) _TECHMAP_REPLACE_ (
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.DIA(32'd0),
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.DIPA(4'd0),
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.DOA(DO[31:0]),
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.DOPA(DOP[3:0]),
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.ADDRA(A1ADDR_14),
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.CLKA(CLK2 ^ !CLKPOL2),
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.ENA(A1EN),
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.REGCEA(|1),
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.RSTA(|0),
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.WEA(4'b0),
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.DIB(DI),
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.DIPB(DIP),
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.DOB(DOB),
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.DOPB(DOPB),
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.ADDRB(B1ADDR_14),
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.CLKB(CLK3 ^ !CLKPOL3),
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.ENB(|1),
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.REGCEB(|0),
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.RSTB(|0),
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.WEB(B1EN_4)
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);
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end else begin
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RAMB16BWER #(
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.DATA_WIDTH_A(CFG_DBITS),
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.DATA_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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`include "brams_init_16.vh"
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) _TECHMAP_REPLACE_ (
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.DIA(32'd0),
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.DIPA(4'd0),
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.DOA(DO[31:0]),
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.DOPA(DOP[3:0]),
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.ADDRA(A1ADDR_14),
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.CLKA(CLK2 ^ !CLKPOL2),
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.ENA(A1EN),
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.REGCEA(|1),
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.RSTA(|0),
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.WEA(4'b0),
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.DIB(DI),
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.DIPB(DIP),
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.DOB(DOB),
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.DOPB(DOPB),
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.ADDRB(B1ADDR_14),
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.CLKB(CLK3 ^ !CLKPOL3),
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.ENB(|1),
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.REGCEB(|0),
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.RSTB(|0),
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.WEB(B1EN_4)
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);
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end endgenerate
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 9;
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parameter CFG_DBITS = 18;
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parameter CFG_ENABLE_B = 2;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [9215:0] INIT = 9216'bx;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input [CFG_ENABLE_B-1:0] B1EN;
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wire [12:0] A1ADDR_13 = A1ADDR << (13 - CFG_ABITS);
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wire [12:0] B1ADDR_13 = B1ADDR << (13 - CFG_ABITS);
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wire [1:0] B1EN_2 = {2{B1EN}};
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [15:0] DOBDO;
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wire [1:0] DOPBDOP;
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assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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generate if (CFG_DBITS > 8) begin
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RAMB8BWER #(
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.RAM_MODE("TDP"),
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.DATA_WIDTH_A(CFG_DBITS),
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.DATA_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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`include "brams_init_9.vh"
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRAWRADDR(A1ADDR_13),
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.CLKAWRCLK(CLK2 ^ !CLKPOL2),
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.ENAWREN(A1EN),
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.REGCEA(|1),
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.RSTA(|0),
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.WEAWEL(2'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBRDADDR(B1ADDR_13),
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.CLKBRDCLK(CLK3 ^ !CLKPOL3),
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.ENBRDEN(|1),
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.REGCEBREGCE(|0),
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.RSTB(|0),
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.WEBWEU(B1EN_2)
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);
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end else begin
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RAMB8BWER #(
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.RAM_MODE("TDP"),
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.DATA_WIDTH_A(CFG_DBITS),
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.DATA_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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`include "brams_init_8.vh"
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRAWRADDR(A1ADDR_13),
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.CLKAWRCLK(CLK2 ^ !CLKPOL2),
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.ENAWREN(A1EN),
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.REGCEA(|1),
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.RSTA(|0),
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.WEAWEL(2'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBRDADDR(B1ADDR_13),
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.CLKBRDCLK(CLK3 ^ !CLKPOL3),
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.ENBRDEN(|1),
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.REGCEBREGCE(|0),
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.RSTB(|0),
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.WEBWEU(B1EN_2)
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);
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end endgenerate
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endmodule
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