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Renamed port access function on RTLIL::Cell, added param access functions

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This commit is contained in:
Clifford Wolf 2014-07-31 16:38:54 +02:00
parent b5a9e51b96
commit cdae8abe16
46 changed files with 1086 additions and 1059 deletions
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6
passes/tests/test_cell.cc
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@ -38,7 +38,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std
RTLIL::Wire *wire = module->addWire("\\A");
wire->width = 1 + xorshift32(8);
wire->port_input = true;
cell->set("\\A", wire);
cell->setPort("\\A", wire);
}
if (cell_type_flags.find('B') != std::string::npos) {
@ -48,7 +48,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std
else
wire->width = 1 + xorshift32(8);
wire->port_input = true;
cell->set("\\B", wire);
cell->setPort("\\B", wire);
}
if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) {
@ -69,7 +69,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std
RTLIL::Wire *wire = module->addWire("\\Y");
wire->width = 1 + xorshift32(8);
wire->port_output = true;
cell->set("\\Y", wire);
cell->setPort("\\Y", wire);
}
module->fixup_ports();